1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 /* 23 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 24 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 25 * consisting of a standard header and a device-specific set of registers. PCI 26 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 27 * other things). Within the PCI configuration space, the GPIOBASE register 28 * tells us where in the device's I/O region we can find more registers to 29 * actually access the GPIOs. 30 * 31 * PCI bus/device/function 0:1f:0 => PCI config registers 32 * PCI config register "GPIOBASE" 33 * PCI I/O space + [GPIOBASE] => start of GPIO registers 34 * GPIO registers => gpio pin function, direction, value 35 * 36 * 37 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 38 * ICH versions have more, but the decoding the matrix that describes them is 39 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 40 * but they will ONLY work for certain unspecified chipsets because the offset 41 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 42 * reserved or subject to arcane restrictions. 43 */ 44 45 #include <common.h> 46 #include <pci.h> 47 #include <asm/gpio.h> 48 #include <asm/io.h> 49 50 /* Where in config space is the register that points to the GPIO registers? */ 51 #define PCI_CFG_GPIOBASE 0x48 52 53 #define NUM_BANKS 3 54 55 /* Within the I/O space, where are the registers to control the GPIOs? */ 56 static struct { 57 u8 use_sel; 58 u8 io_sel; 59 u8 lvl; 60 } gpio_bank[NUM_BANKS] = { 61 { 0x00, 0x04, 0x0c }, /* Bank 0 */ 62 { 0x30, 0x34, 0x38 }, /* Bank 1 */ 63 { 0x40, 0x44, 0x48 } /* Bank 2 */ 64 }; 65 66 static pci_dev_t dev; /* handle for 0:1f:0 */ 67 static u32 gpiobase; /* offset into I/O space */ 68 static int found_it_once; /* valid GPIO device? */ 69 static u32 lock[NUM_BANKS]; /* "lock" for access to pins */ 70 71 static int bad_arg(int num, int *bank, int *bitnum) 72 { 73 int i = num / 32; 74 int j = num % 32; 75 76 if (num < 0 || i > NUM_BANKS) { 77 debug("%s: bogus gpio num: %d\n", __func__, num); 78 return -1; 79 } 80 *bank = i; 81 *bitnum = j; 82 return 0; 83 } 84 85 static int mark_gpio(int bank, int bitnum) 86 { 87 if (lock[bank] & (1UL << bitnum)) { 88 debug("%s: %d.%d already marked\n", __func__, bank, bitnum); 89 return -1; 90 } 91 lock[bank] |= (1 << bitnum); 92 return 0; 93 } 94 95 static void clear_gpio(int bank, int bitnum) 96 { 97 lock[bank] &= ~(1 << bitnum); 98 } 99 100 static int notmine(int num, int *bank, int *bitnum) 101 { 102 if (bad_arg(num, bank, bitnum)) 103 return -1; 104 return !(lock[*bank] & (1UL << *bitnum)); 105 } 106 107 static int gpio_init(void) 108 { 109 u8 tmpbyte; 110 u16 tmpword; 111 u32 tmplong; 112 113 /* Have we already done this? */ 114 if (found_it_once) 115 return 0; 116 117 /* Where should it be? */ 118 dev = PCI_BDF(0, 0x1f, 0); 119 120 /* Is the device present? */ 121 pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword); 122 if (tmpword != PCI_VENDOR_ID_INTEL) { 123 debug("%s: wrong VendorID\n", __func__); 124 return -1; 125 } 126 127 pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword); 128 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 129 /* 130 * We'd like to validate the Device ID too, but pretty much any 131 * value is either a) correct with slight differences, or b) 132 * correct but undocumented. We'll have to check a bunch of other 133 * things instead... 134 */ 135 136 /* I/O should already be enabled (it's a RO bit). */ 137 pci_read_config_word(dev, PCI_COMMAND, &tmpword); 138 if (!(tmpword & PCI_COMMAND_IO)) { 139 debug("%s: device IO not enabled\n", __func__); 140 return -1; 141 } 142 143 /* Header Type must be normal (bits 6-0 only; see spec.) */ 144 pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte); 145 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 146 debug("%s: invalid Header type\n", __func__); 147 return -1; 148 } 149 150 /* Base Class must be a bridge device */ 151 pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte); 152 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 153 debug("%s: invalid class\n", __func__); 154 return -1; 155 } 156 /* Sub Class must be ISA */ 157 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte); 158 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 159 debug("%s: invalid subclass\n", __func__); 160 return -1; 161 } 162 163 /* Programming Interface must be 0x00 (no others exist) */ 164 pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte); 165 if (tmpbyte != 0x00) { 166 debug("%s: invalid interface type\n", __func__); 167 return -1; 168 } 169 170 /* 171 * GPIOBASE moved to its current offset with ICH6, but prior to 172 * that it was unused (or undocumented). Check that it looks 173 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 174 */ 175 pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong); 176 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 177 !(tmplong & 0x00000001)) { 178 debug("%s: unexpected GPIOBASE value\n", __func__); 179 return -1; 180 } 181 182 /* 183 * Okay, I guess we're looking at the right device. The actual 184 * GPIO registers are in the PCI device's I/O space, starting 185 * at the offset that we just read. Bit 0 indicates that it's 186 * an I/O address, not a memory address, so mask that off. 187 */ 188 gpiobase = tmplong & 0xfffffffe; 189 190 /* Finally. These are the droids we're looking for. */ 191 found_it_once = 1; 192 return 0; 193 } 194 195 int gpio_request(unsigned num, const char *label /* UNUSED */) 196 { 197 u32 tmplong; 198 int i = 0, j = 0; 199 200 /* Is the hardware ready? */ 201 if (gpio_init()) 202 return -1; 203 204 if (bad_arg(num, &i, &j)) 205 return -1; 206 207 /* 208 * Make sure that the GPIO pin we want isn't already in use for some 209 * built-in hardware function. We have to check this for every 210 * requested pin. 211 */ 212 tmplong = inl(gpiobase + gpio_bank[i].use_sel); 213 if (!(tmplong & (1UL << j))) { 214 debug("%s: gpio %d is reserved for internal use\n", __func__, 215 num); 216 return -1; 217 } 218 219 return mark_gpio(i, j); 220 } 221 222 int gpio_free(unsigned num) 223 { 224 int i = 0, j = 0; 225 226 if (notmine(num, &i, &j)) 227 return -1; 228 229 clear_gpio(i, j); 230 return 0; 231 } 232 233 int gpio_direction_input(unsigned num) 234 { 235 u32 tmplong; 236 int i = 0, j = 0; 237 238 if (notmine(num, &i, &j)) 239 return -1; 240 241 tmplong = inl(gpiobase + gpio_bank[i].io_sel); 242 tmplong |= (1UL << j); 243 outl(gpiobase + gpio_bank[i].io_sel, tmplong); 244 return 0; 245 } 246 247 int gpio_direction_output(unsigned num, int value) 248 { 249 u32 tmplong; 250 int i = 0, j = 0; 251 252 if (notmine(num, &i, &j)) 253 return -1; 254 255 tmplong = inl(gpiobase + gpio_bank[i].io_sel); 256 tmplong &= ~(1UL << j); 257 outl(gpiobase + gpio_bank[i].io_sel, tmplong); 258 return 0; 259 } 260 261 int gpio_get_value(unsigned num) 262 { 263 u32 tmplong; 264 int i = 0, j = 0; 265 int r; 266 267 if (notmine(num, &i, &j)) 268 return -1; 269 270 tmplong = inl(gpiobase + gpio_bank[i].lvl); 271 r = (tmplong & (1UL << j)) ? 1 : 0; 272 return r; 273 } 274 275 int gpio_set_value(unsigned num, int value) 276 { 277 u32 tmplong; 278 int i = 0, j = 0; 279 280 if (notmine(num, &i, &j)) 281 return -1; 282 283 tmplong = inl(gpiobase + gpio_bank[i].lvl); 284 if (value) 285 tmplong |= (1UL << j); 286 else 287 tmplong &= ~(1UL << j); 288 outl(gpiobase + gpio_bank[i].lvl, tmplong); 289 return 0; 290 } 291