1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <pci.h> 31 #include <asm/gpio.h> 32 #include <asm/io.h> 33 34 /* Where in config space is the register that points to the GPIO registers? */ 35 #define PCI_CFG_GPIOBASE 0x48 36 37 #define NUM_BANKS 3 38 39 /* Within the I/O space, where are the registers to control the GPIOs? */ 40 static struct { 41 u8 use_sel; 42 u8 io_sel; 43 u8 lvl; 44 } gpio_bank[NUM_BANKS] = { 45 { 0x00, 0x04, 0x0c }, /* Bank 0 */ 46 { 0x30, 0x34, 0x38 }, /* Bank 1 */ 47 { 0x40, 0x44, 0x48 } /* Bank 2 */ 48 }; 49 50 static pci_dev_t dev; /* handle for 0:1f:0 */ 51 static u32 gpiobase; /* offset into I/O space */ 52 static int found_it_once; /* valid GPIO device? */ 53 static u32 lock[NUM_BANKS]; /* "lock" for access to pins */ 54 55 static int bad_arg(int num, int *bank, int *bitnum) 56 { 57 int i = num / 32; 58 int j = num % 32; 59 60 if (num < 0 || i > NUM_BANKS) { 61 debug("%s: bogus gpio num: %d\n", __func__, num); 62 return -1; 63 } 64 *bank = i; 65 *bitnum = j; 66 return 0; 67 } 68 69 static int mark_gpio(int bank, int bitnum) 70 { 71 if (lock[bank] & (1UL << bitnum)) { 72 debug("%s: %d.%d already marked\n", __func__, bank, bitnum); 73 return -1; 74 } 75 lock[bank] |= (1 << bitnum); 76 return 0; 77 } 78 79 static void clear_gpio(int bank, int bitnum) 80 { 81 lock[bank] &= ~(1 << bitnum); 82 } 83 84 static int notmine(int num, int *bank, int *bitnum) 85 { 86 if (bad_arg(num, bank, bitnum)) 87 return -1; 88 return !(lock[*bank] & (1UL << *bitnum)); 89 } 90 91 static int gpio_init(void) 92 { 93 u8 tmpbyte; 94 u16 tmpword; 95 u32 tmplong; 96 97 /* Have we already done this? */ 98 if (found_it_once) 99 return 0; 100 101 /* Where should it be? */ 102 dev = PCI_BDF(0, 0x1f, 0); 103 104 /* Is the device present? */ 105 pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword); 106 if (tmpword != PCI_VENDOR_ID_INTEL) { 107 debug("%s: wrong VendorID\n", __func__); 108 return -1; 109 } 110 111 pci_read_config_word(dev, PCI_DEVICE_ID, &tmpword); 112 debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); 113 /* 114 * We'd like to validate the Device ID too, but pretty much any 115 * value is either a) correct with slight differences, or b) 116 * correct but undocumented. We'll have to check a bunch of other 117 * things instead... 118 */ 119 120 /* I/O should already be enabled (it's a RO bit). */ 121 pci_read_config_word(dev, PCI_COMMAND, &tmpword); 122 if (!(tmpword & PCI_COMMAND_IO)) { 123 debug("%s: device IO not enabled\n", __func__); 124 return -1; 125 } 126 127 /* Header Type must be normal (bits 6-0 only; see spec.) */ 128 pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte); 129 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 130 debug("%s: invalid Header type\n", __func__); 131 return -1; 132 } 133 134 /* Base Class must be a bridge device */ 135 pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte); 136 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 137 debug("%s: invalid class\n", __func__); 138 return -1; 139 } 140 /* Sub Class must be ISA */ 141 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte); 142 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 143 debug("%s: invalid subclass\n", __func__); 144 return -1; 145 } 146 147 /* Programming Interface must be 0x00 (no others exist) */ 148 pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte); 149 if (tmpbyte != 0x00) { 150 debug("%s: invalid interface type\n", __func__); 151 return -1; 152 } 153 154 /* 155 * GPIOBASE moved to its current offset with ICH6, but prior to 156 * that it was unused (or undocumented). Check that it looks 157 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 158 */ 159 pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong); 160 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 161 !(tmplong & 0x00000001)) { 162 debug("%s: unexpected GPIOBASE value\n", __func__); 163 return -1; 164 } 165 166 /* 167 * Okay, I guess we're looking at the right device. The actual 168 * GPIO registers are in the PCI device's I/O space, starting 169 * at the offset that we just read. Bit 0 indicates that it's 170 * an I/O address, not a memory address, so mask that off. 171 */ 172 gpiobase = tmplong & 0xfffffffe; 173 174 /* Finally. These are the droids we're looking for. */ 175 found_it_once = 1; 176 return 0; 177 } 178 179 int gpio_request(unsigned num, const char *label /* UNUSED */) 180 { 181 u32 tmplong; 182 int i = 0, j = 0; 183 184 /* Is the hardware ready? */ 185 if (gpio_init()) 186 return -1; 187 188 if (bad_arg(num, &i, &j)) 189 return -1; 190 191 /* 192 * Make sure that the GPIO pin we want isn't already in use for some 193 * built-in hardware function. We have to check this for every 194 * requested pin. 195 */ 196 tmplong = inl(gpiobase + gpio_bank[i].use_sel); 197 if (!(tmplong & (1UL << j))) { 198 debug("%s: gpio %d is reserved for internal use\n", __func__, 199 num); 200 return -1; 201 } 202 203 return mark_gpio(i, j); 204 } 205 206 int gpio_free(unsigned num) 207 { 208 int i = 0, j = 0; 209 210 if (notmine(num, &i, &j)) 211 return -1; 212 213 clear_gpio(i, j); 214 return 0; 215 } 216 217 int gpio_direction_input(unsigned num) 218 { 219 u32 tmplong; 220 int i = 0, j = 0; 221 222 if (notmine(num, &i, &j)) 223 return -1; 224 225 tmplong = inl(gpiobase + gpio_bank[i].io_sel); 226 tmplong |= (1UL << j); 227 outl(gpiobase + gpio_bank[i].io_sel, tmplong); 228 return 0; 229 } 230 231 int gpio_direction_output(unsigned num, int value) 232 { 233 u32 tmplong; 234 int i = 0, j = 0; 235 236 if (notmine(num, &i, &j)) 237 return -1; 238 239 tmplong = inl(gpiobase + gpio_bank[i].io_sel); 240 tmplong &= ~(1UL << j); 241 outl(gpiobase + gpio_bank[i].io_sel, tmplong); 242 return 0; 243 } 244 245 int gpio_get_value(unsigned num) 246 { 247 u32 tmplong; 248 int i = 0, j = 0; 249 int r; 250 251 if (notmine(num, &i, &j)) 252 return -1; 253 254 tmplong = inl(gpiobase + gpio_bank[i].lvl); 255 r = (tmplong & (1UL << j)) ? 1 : 0; 256 return r; 257 } 258 259 int gpio_set_value(unsigned num, int value) 260 { 261 u32 tmplong; 262 int i = 0, j = 0; 263 264 if (notmine(num, &i, &j)) 265 return -1; 266 267 tmplong = inl(gpiobase + gpio_bank[i].lvl); 268 if (value) 269 tmplong |= (1UL << j); 270 else 271 tmplong &= ~(1UL << j); 272 outl(gpiobase + gpio_bank[i].lvl, tmplong); 273 return 0; 274 } 275