1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 /* 7 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 8 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 9 * consisting of a standard header and a device-specific set of registers. PCI 10 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 11 * other things). Within the PCI configuration space, the GPIOBASE register 12 * tells us where in the device's I/O region we can find more registers to 13 * actually access the GPIOs. 14 * 15 * PCI bus/device/function 0:1f:0 => PCI config registers 16 * PCI config register "GPIOBASE" 17 * PCI I/O space + [GPIOBASE] => start of GPIO registers 18 * GPIO registers => gpio pin function, direction, value 19 * 20 * 21 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most 22 * ICH versions have more, but the decoding the matrix that describes them is 23 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, 24 * but they will ONLY work for certain unspecified chipsets because the offset 25 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or 26 * reserved or subject to arcane restrictions. 27 */ 28 29 #include <common.h> 30 #include <dm.h> 31 #include <errno.h> 32 #include <fdtdec.h> 33 #include <pch.h> 34 #include <pci.h> 35 #include <syscon.h> 36 #include <asm/cpu.h> 37 #include <asm/gpio.h> 38 #include <asm/io.h> 39 #include <asm/pci.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 #define GPIO_PER_BANK 32 44 45 struct ich6_bank_priv { 46 /* These are I/O addresses */ 47 uint16_t use_sel; 48 uint16_t io_sel; 49 uint16_t lvl; 50 }; 51 52 #define GPIO_USESEL_OFFSET(x) (x) 53 #define GPIO_IOSEL_OFFSET(x) (x + 4) 54 #define GPIO_LVL_OFFSET(x) (x + 8) 55 56 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value) 57 { 58 u32 val; 59 60 val = inl(base); 61 if (value) 62 val |= (1UL << offset); 63 else 64 val &= ~(1UL << offset); 65 outl(val, base); 66 67 return 0; 68 } 69 70 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir) 71 { 72 u32 val; 73 74 if (!dir) { 75 val = inl(base); 76 val |= (1UL << offset); 77 outl(val, base); 78 } else { 79 val = inl(base); 80 val &= ~(1UL << offset); 81 outl(val, base); 82 } 83 84 return 0; 85 } 86 87 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) 88 { 89 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 90 u32 gpiobase; 91 int offset; 92 int ret; 93 94 ret = pch_get_gpio_base(dev->parent, &gpiobase); 95 if (ret) 96 return ret; 97 98 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); 99 if (offset == -1) { 100 debug("%s: Invalid register offset %d\n", __func__, offset); 101 return -EINVAL; 102 } 103 plat->offset = offset; 104 plat->base_addr = gpiobase + offset; 105 plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, 106 "bank-name", NULL); 107 108 return 0; 109 } 110 111 static int ich6_gpio_probe(struct udevice *dev) 112 { 113 struct ich6_bank_platdata *plat = dev_get_platdata(dev); 114 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 115 struct ich6_bank_priv *bank = dev_get_priv(dev); 116 struct udevice *pinctrl; 117 int ret; 118 119 /* Set up pin control if available */ 120 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl); 121 debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret); 122 123 uc_priv->gpio_count = GPIO_PER_BANK; 124 uc_priv->bank_name = plat->bank_name; 125 bank->use_sel = plat->base_addr; 126 bank->io_sel = plat->base_addr + 4; 127 bank->lvl = plat->base_addr + 8; 128 129 return 0; 130 } 131 132 static int ich6_gpio_request(struct udevice *dev, unsigned offset, 133 const char *label) 134 { 135 struct ich6_bank_priv *bank = dev_get_priv(dev); 136 u32 tmplong; 137 138 /* 139 * Make sure that the GPIO pin we want isn't already in use for some 140 * built-in hardware function. We have to check this for every 141 * requested pin. 142 */ 143 tmplong = inl(bank->use_sel); 144 if (!(tmplong & (1UL << offset))) { 145 debug("%s: gpio %d is reserved for internal use\n", __func__, 146 offset); 147 return -EPERM; 148 } 149 150 return 0; 151 } 152 153 static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) 154 { 155 struct ich6_bank_priv *bank = dev_get_priv(dev); 156 157 return _ich6_gpio_set_direction(bank->io_sel, offset, 0); 158 } 159 160 static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, 161 int value) 162 { 163 int ret; 164 struct ich6_bank_priv *bank = dev_get_priv(dev); 165 166 ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1); 167 if (ret) 168 return ret; 169 170 return _ich6_gpio_set_value(bank->lvl, offset, value); 171 } 172 173 static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) 174 { 175 struct ich6_bank_priv *bank = dev_get_priv(dev); 176 u32 tmplong; 177 int r; 178 179 tmplong = inl(bank->lvl); 180 r = (tmplong & (1UL << offset)) ? 1 : 0; 181 return r; 182 } 183 184 static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, 185 int value) 186 { 187 struct ich6_bank_priv *bank = dev_get_priv(dev); 188 return _ich6_gpio_set_value(bank->lvl, offset, value); 189 } 190 191 static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) 192 { 193 struct ich6_bank_priv *bank = dev_get_priv(dev); 194 u32 mask = 1UL << offset; 195 196 if (!(inl(bank->use_sel) & mask)) 197 return GPIOF_FUNC; 198 if (inl(bank->io_sel) & mask) 199 return GPIOF_INPUT; 200 else 201 return GPIOF_OUTPUT; 202 } 203 204 static const struct dm_gpio_ops gpio_ich6_ops = { 205 .request = ich6_gpio_request, 206 .direction_input = ich6_gpio_direction_input, 207 .direction_output = ich6_gpio_direction_output, 208 .get_value = ich6_gpio_get_value, 209 .set_value = ich6_gpio_set_value, 210 .get_function = ich6_gpio_get_function, 211 }; 212 213 static const struct udevice_id intel_ich6_gpio_ids[] = { 214 { .compatible = "intel,ich6-gpio" }, 215 { } 216 }; 217 218 U_BOOT_DRIVER(gpio_ich6) = { 219 .name = "gpio_ich6", 220 .id = UCLASS_GPIO, 221 .of_match = intel_ich6_gpio_ids, 222 .ops = &gpio_ich6_ops, 223 .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, 224 .probe = ich6_gpio_probe, 225 .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), 226 .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), 227 }; 228