1 /* 2 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <asm/gpio.h> 12 #include <asm/io.h> 13 14 #define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ 15 #define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ 16 #define GPIO_OUTDT 0x08 /* General Output Register */ 17 #define GPIO_INDT 0x0c /* General Input Register */ 18 #define GPIO_INTDT 0x10 /* Interrupt Display Register */ 19 #define GPIO_INTCLR 0x14 /* Interrupt Clear Register */ 20 #define GPIO_INTMSK 0x18 /* Interrupt Mask Register */ 21 #define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */ 22 #define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */ 23 #define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ 24 #define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ 25 #define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ 26 27 #define RCAR_MAX_GPIO_PER_BANK 32 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 struct rcar_gpio_priv { 32 void __iomem *regs; 33 }; 34 35 static int rcar_gpio_get_value(struct udevice *dev, unsigned offset) 36 { 37 struct rcar_gpio_priv *priv = dev_get_priv(dev); 38 const u32 bit = BIT(offset); 39 40 /* 41 * Testing on r8a7790 shows that INDT does not show correct pin state 42 * when configured as output, so use OUTDT in case of output pins. 43 */ 44 if (readl(priv->regs + GPIO_INOUTSEL) & bit) 45 return !!(readl(priv->regs + GPIO_OUTDT) & bit); 46 else 47 return !!(readl(priv->regs + GPIO_INDT) & bit); 48 } 49 50 static int rcar_gpio_set_value(struct udevice *dev, unsigned offset, 51 int value) 52 { 53 struct rcar_gpio_priv *priv = dev_get_priv(dev); 54 55 if (value) 56 setbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); 57 else 58 clrbits_le32(priv->regs + GPIO_OUTDT, BIT(offset)); 59 60 return 0; 61 } 62 63 static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset, 64 bool output) 65 { 66 /* 67 * follow steps in the GPIO documentation for 68 * "Setting General Output Mode" and 69 * "Setting General Input Mode" 70 */ 71 72 /* Configure postive logic in POSNEG */ 73 clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); 74 75 /* Select "General Input/Output Mode" in IOINTSEL */ 76 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); 77 78 /* Select Input Mode or Output Mode in INOUTSEL */ 79 if (output) 80 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); 81 else 82 clrbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); 83 } 84 85 static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset) 86 { 87 struct rcar_gpio_priv *priv = dev_get_priv(dev); 88 89 rcar_gpio_set_direction(priv->regs, offset, false); 90 91 return 0; 92 } 93 94 static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset, 95 int value) 96 { 97 struct rcar_gpio_priv *priv = dev_get_priv(dev); 98 99 /* write GPIO value to output before selecting output mode of pin */ 100 rcar_gpio_set_value(dev, offset, value); 101 rcar_gpio_set_direction(priv->regs, offset, true); 102 103 return 0; 104 } 105 106 static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) 107 { 108 struct rcar_gpio_priv *priv = dev_get_priv(dev); 109 110 if (readl(priv->regs + GPIO_INOUTSEL) & BIT(offset)) 111 return GPIOF_OUTPUT; 112 else 113 return GPIOF_INPUT; 114 } 115 116 static const struct dm_gpio_ops rcar_gpio_ops = { 117 .direction_input = rcar_gpio_direction_input, 118 .direction_output = rcar_gpio_direction_output, 119 .get_value = rcar_gpio_get_value, 120 .set_value = rcar_gpio_set_value, 121 .get_function = rcar_gpio_get_function, 122 }; 123 124 static int rcar_gpio_probe(struct udevice *dev) 125 { 126 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 127 struct rcar_gpio_priv *priv = dev_get_priv(dev); 128 struct fdtdec_phandle_args args; 129 struct clk clk; 130 int node = dev_of_offset(dev); 131 int ret; 132 133 priv->regs = (void __iomem *)devfdt_get_addr(dev); 134 uc_priv->bank_name = dev->name; 135 136 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", 137 NULL, 3, 0, &args); 138 uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; 139 140 ret = clk_get_by_index(dev, 0, &clk); 141 if (ret < 0) { 142 dev_err(dev, "Failed to get GPIO bank clock\n"); 143 return ret; 144 } 145 146 ret = clk_enable(&clk); 147 clk_free(&clk); 148 if (ret) { 149 dev_err(dev, "Failed to enable GPIO bank clock\n"); 150 return ret; 151 } 152 153 return 0; 154 } 155 156 static const struct udevice_id rcar_gpio_ids[] = { 157 { .compatible = "renesas,gpio-r8a7795" }, 158 { .compatible = "renesas,gpio-r8a7796" }, 159 { /* sentinel */ } 160 }; 161 162 U_BOOT_DRIVER(rcar_gpio) = { 163 .name = "rcar-gpio", 164 .id = UCLASS_GPIO, 165 .of_match = rcar_gpio_ids, 166 .ops = &rcar_gpio_ops, 167 .priv_auto_alloc_size = sizeof(struct rcar_gpio_priv), 168 .probe = rcar_gpio_probe, 169 }; 170