1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2015 Marek Vasut <marex@denx.de> 4 * 5 * DesignWare APB GPIO driver 6 */ 7 8 #include <common.h> 9 #include <malloc.h> 10 #include <asm/arch/gpio.h> 11 #include <asm/gpio.h> 12 #include <asm/io.h> 13 #include <dm.h> 14 #include <dm/device-internal.h> 15 #include <dm/lists.h> 16 #include <dm/root.h> 17 #include <errno.h> 18 #include <reset.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc) 23 #define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc) 24 #define GPIO_INTEN 0x30 25 #define GPIO_INTMASK 0x34 26 #define GPIO_INTTYPE_LEVEL 0x38 27 #define GPIO_INT_POLARITY 0x3c 28 #define GPIO_INTSTATUS 0x40 29 #define GPIO_PORTA_DEBOUNCE 0x48 30 #define GPIO_PORTA_EOI 0x4c 31 #define GPIO_EXT_PORT(p) (0x50 + (p) * 4) 32 33 struct gpio_dwapb_priv { 34 struct reset_ctl_bulk resets; 35 }; 36 37 struct gpio_dwapb_platdata { 38 const char *name; 39 int bank; 40 int pins; 41 fdt_addr_t base; 42 }; 43 44 static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin) 45 { 46 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 47 48 clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); 49 return 0; 50 } 51 52 static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin, 53 int val) 54 { 55 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 56 57 setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin); 58 59 if (val) 60 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 61 else 62 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 63 64 return 0; 65 } 66 67 static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin) 68 { 69 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 70 return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin)); 71 } 72 73 74 static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val) 75 { 76 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 77 78 if (val) 79 setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 80 else 81 clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin); 82 83 return 0; 84 } 85 86 static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset) 87 { 88 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 89 u32 gpio; 90 91 gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank)); 92 93 if (gpio & BIT(offset)) 94 return GPIOF_OUTPUT; 95 else 96 return GPIOF_INPUT; 97 } 98 99 static const struct dm_gpio_ops gpio_dwapb_ops = { 100 .direction_input = dwapb_gpio_direction_input, 101 .direction_output = dwapb_gpio_direction_output, 102 .get_value = dwapb_gpio_get_value, 103 .set_value = dwapb_gpio_set_value, 104 .get_function = dwapb_gpio_get_function, 105 }; 106 107 static int gpio_dwapb_reset(struct udevice *dev) 108 { 109 int ret; 110 struct gpio_dwapb_priv *priv = dev_get_priv(dev); 111 112 ret = reset_get_bulk(dev, &priv->resets); 113 if (ret) { 114 /* Return 0 if error due to !CONFIG_DM_RESET and reset 115 * DT property is not present. 116 */ 117 if (ret == -ENOENT || ret == -ENOTSUPP) 118 return 0; 119 120 dev_warn(dev, "Can't get reset: %d\n", ret); 121 return ret; 122 } 123 124 ret = reset_deassert_bulk(&priv->resets); 125 if (ret) { 126 reset_release_bulk(&priv->resets); 127 dev_err(dev, "Failed to reset: %d\n", ret); 128 return ret; 129 } 130 131 return 0; 132 } 133 134 static int gpio_dwapb_probe(struct udevice *dev) 135 { 136 struct gpio_dev_priv *priv = dev_get_uclass_priv(dev); 137 struct gpio_dwapb_platdata *plat = dev->platdata; 138 139 if (!plat) { 140 /* Reset on parent device only */ 141 return gpio_dwapb_reset(dev); 142 } 143 144 priv->gpio_count = plat->pins; 145 priv->bank_name = plat->name; 146 147 return 0; 148 } 149 150 static int gpio_dwapb_bind(struct udevice *dev) 151 { 152 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 153 const void *blob = gd->fdt_blob; 154 struct udevice *subdev; 155 fdt_addr_t base; 156 int ret, node, bank = 0; 157 158 /* If this is a child device, there is nothing to do here */ 159 if (plat) 160 return 0; 161 162 base = dev_read_addr(dev); 163 if (base == FDT_ADDR_T_NONE) { 164 debug("Can't get the GPIO register base address\n"); 165 return -ENXIO; 166 } 167 168 for (node = fdt_first_subnode(blob, dev_of_offset(dev)); 169 node > 0; 170 node = fdt_next_subnode(blob, node)) { 171 if (!fdtdec_get_bool(blob, node, "gpio-controller")) 172 continue; 173 174 plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL); 175 if (!plat) 176 return -ENOMEM; 177 178 plat->base = base; 179 plat->bank = bank; 180 plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0); 181 plat->name = fdt_stringlist_get(blob, node, "bank-name", 0, 182 NULL); 183 if (!plat->name) { 184 /* 185 * Fall back to node name. This means accessing pins 186 * via bank name won't work. 187 */ 188 plat->name = fdt_get_name(blob, node, NULL); 189 } 190 191 ret = device_bind(dev, dev->driver, plat->name, 192 plat, -1, &subdev); 193 if (ret) 194 return ret; 195 196 dev_set_of_offset(subdev, node); 197 bank++; 198 } 199 200 return 0; 201 } 202 203 static int gpio_dwapb_remove(struct udevice *dev) 204 { 205 struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); 206 struct gpio_dwapb_priv *priv = dev_get_priv(dev); 207 208 if (!plat && priv) 209 return reset_release_bulk(&priv->resets); 210 211 return 0; 212 } 213 214 static const struct udevice_id gpio_dwapb_ids[] = { 215 { .compatible = "snps,dw-apb-gpio" }, 216 { } 217 }; 218 219 U_BOOT_DRIVER(gpio_dwapb) = { 220 .name = "gpio-dwapb", 221 .id = UCLASS_GPIO, 222 .of_match = gpio_dwapb_ids, 223 .ops = &gpio_dwapb_ops, 224 .bind = gpio_dwapb_bind, 225 .probe = gpio_dwapb_probe, 226 .remove = gpio_dwapb_remove, 227 .priv_auto_alloc_size = sizeof(struct gpio_dwapb_priv), 228 }; 229