1 /* 2 * (C) Copyright 2012-2013, Xilinx, Michal Simek 3 * 4 * (C) Copyright 2012 5 * Joe Hershberger <joe.hershberger@ni.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <zynqpl.h> 13 #include <linux/sizes.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/sys_proto.h> 16 17 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 18 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 19 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 20 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 21 #define DEVCFG_ISR_DMA_DONE 0x00002000 22 #define DEVCFG_ISR_PCFG_DONE 0x00000004 23 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 24 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 25 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 26 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 27 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 28 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 29 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 30 31 #ifndef CONFIG_SYS_FPGA_WAIT 32 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ 33 #endif 34 35 #ifndef CONFIG_SYS_FPGA_PROG_TIME 36 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ 37 #endif 38 39 static int zynq_info(xilinx_desc *desc) 40 { 41 return FPGA_SUCCESS; 42 } 43 44 #define DUMMY_WORD 0xffffffff 45 46 /* Xilinx binary format header */ 47 static const u32 bin_format[] = { 48 DUMMY_WORD, /* Dummy words */ 49 DUMMY_WORD, 50 DUMMY_WORD, 51 DUMMY_WORD, 52 DUMMY_WORD, 53 DUMMY_WORD, 54 DUMMY_WORD, 55 DUMMY_WORD, 56 0x000000bb, /* Sync word */ 57 0x11220044, /* Sync word */ 58 DUMMY_WORD, 59 DUMMY_WORD, 60 0xaa995566, /* Sync word */ 61 }; 62 63 #define SWAP_NO 1 64 #define SWAP_DONE 2 65 66 /* 67 * Load the whole word from unaligned buffer 68 * Keep in your mind that it is byte loading on little-endian system 69 */ 70 static u32 load_word(const void *buf, u32 swap) 71 { 72 u32 word = 0; 73 u8 *bitc = (u8 *)buf; 74 int p; 75 76 if (swap == SWAP_NO) { 77 for (p = 0; p < 4; p++) { 78 word <<= 8; 79 word |= bitc[p]; 80 } 81 } else { 82 for (p = 3; p >= 0; p--) { 83 word <<= 8; 84 word |= bitc[p]; 85 } 86 } 87 88 return word; 89 } 90 91 static u32 check_header(const void *buf) 92 { 93 u32 i, pattern; 94 int swap = SWAP_NO; 95 u32 *test = (u32 *)buf; 96 97 debug("%s: Let's check bitstream header\n", __func__); 98 99 /* Checking that passing bin is not a bitstream */ 100 for (i = 0; i < ARRAY_SIZE(bin_format); i++) { 101 pattern = load_word(&test[i], swap); 102 103 /* 104 * Bitstreams in binary format are swapped 105 * compare to regular bistream. 106 * Do not swap dummy word but if swap is done assume 107 * that parsing buffer is binary format 108 */ 109 if ((__swab32(pattern) != DUMMY_WORD) && 110 (__swab32(pattern) == bin_format[i])) { 111 pattern = __swab32(pattern); 112 swap = SWAP_DONE; 113 debug("%s: data swapped - let's swap\n", __func__); 114 } 115 116 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, 117 (u32)&test[i], pattern, bin_format[i]); 118 if (pattern != bin_format[i]) { 119 debug("%s: Bitstream is not recognized\n", __func__); 120 return 0; 121 } 122 } 123 debug("%s: Found bitstream header at %x %s swapinng\n", __func__, 124 (u32)buf, swap == SWAP_NO ? "without" : "with"); 125 126 return swap; 127 } 128 129 static void *check_data(u8 *buf, size_t bsize, u32 *swap) 130 { 131 u32 word, p = 0; /* possition */ 132 133 /* Because buf doesn't need to be aligned let's read it by chars */ 134 for (p = 0; p < bsize; p++) { 135 word = load_word(&buf[p], SWAP_NO); 136 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); 137 138 /* Find the first bitstream dummy word */ 139 if (word == DUMMY_WORD) { 140 debug("%s: Found dummy word at position %x/%x\n", 141 __func__, p, (u32)&buf[p]); 142 *swap = check_header(&buf[p]); 143 if (*swap) { 144 /* FIXME add full bitstream checking here */ 145 return &buf[p]; 146 } 147 } 148 /* Loop can be huge - support CTRL + C */ 149 if (ctrlc()) 150 return NULL; 151 } 152 return NULL; 153 } 154 155 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) 156 { 157 unsigned long ts; 158 u32 isr_status; 159 160 /* Set up the transfer */ 161 writel((u32)srcbuf, &devcfg_base->dma_src_addr); 162 writel(dstbuf, &devcfg_base->dma_dst_addr); 163 writel(srclen, &devcfg_base->dma_src_len); 164 writel(dstlen, &devcfg_base->dma_dst_len); 165 166 isr_status = readl(&devcfg_base->int_sts); 167 168 /* Polling the PCAP_INIT status for Set */ 169 ts = get_timer(0); 170 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { 171 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { 172 debug("%s: Error: isr = 0x%08X\n", __func__, 173 isr_status); 174 debug("%s: Write count = 0x%08X\n", __func__, 175 readl(&devcfg_base->write_count)); 176 debug("%s: Read count = 0x%08X\n", __func__, 177 readl(&devcfg_base->read_count)); 178 179 return FPGA_FAIL; 180 } 181 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { 182 printf("%s: Timeout wait for DMA to complete\n", 183 __func__); 184 return FPGA_FAIL; 185 } 186 isr_status = readl(&devcfg_base->int_sts); 187 } 188 189 debug("%s: DMA transfer is done\n", __func__); 190 191 /* Clear out the DMA status */ 192 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 193 194 return FPGA_SUCCESS; 195 } 196 197 static int zynq_dma_xfer_init(u32 partialbit) 198 { 199 u32 status, control, isr_status; 200 unsigned long ts; 201 202 /* Clear loopback bit */ 203 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); 204 205 if (!partialbit) { 206 zynq_slcr_devcfg_disable(); 207 208 /* Setting PCFG_PROG_B signal to high */ 209 control = readl(&devcfg_base->ctrl); 210 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 211 /* Setting PCFG_PROG_B signal to low */ 212 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 213 214 /* Polling the PCAP_INIT status for Reset */ 215 ts = get_timer(0); 216 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { 217 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 218 printf("%s: Timeout wait for INIT to clear\n", 219 __func__); 220 return FPGA_FAIL; 221 } 222 } 223 224 /* Setting PCFG_PROG_B signal to high */ 225 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 226 227 /* Polling the PCAP_INIT status for Set */ 228 ts = get_timer(0); 229 while (!(readl(&devcfg_base->status) & 230 DEVCFG_STATUS_PCFG_INIT)) { 231 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 232 printf("%s: Timeout wait for INIT to set\n", 233 __func__); 234 return FPGA_FAIL; 235 } 236 } 237 } 238 239 isr_status = readl(&devcfg_base->int_sts); 240 241 /* Clear it all, so if Boot ROM comes back, it can proceed */ 242 writel(0xFFFFFFFF, &devcfg_base->int_sts); 243 244 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { 245 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); 246 247 /* If RX FIFO overflow, need to flush RX FIFO first */ 248 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { 249 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); 250 writel(0xFFFFFFFF, &devcfg_base->int_sts); 251 } 252 return FPGA_FAIL; 253 } 254 255 status = readl(&devcfg_base->status); 256 257 debug("%s: Status = 0x%08X\n", __func__, status); 258 259 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { 260 debug("%s: Error: device busy\n", __func__); 261 return FPGA_FAIL; 262 } 263 264 debug("%s: Device ready\n", __func__); 265 266 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { 267 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { 268 /* Error state, transfer cannot occur */ 269 debug("%s: ISR indicates error\n", __func__); 270 return FPGA_FAIL; 271 } else { 272 /* Clear out the status */ 273 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 274 } 275 } 276 277 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { 278 /* Clear the count of completed DMA transfers */ 279 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); 280 } 281 282 return FPGA_SUCCESS; 283 } 284 285 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) 286 { 287 u32 *new_buf; 288 u32 i; 289 290 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { 291 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); 292 293 /* 294 * This might be dangerous but permits to flash if 295 * ARCH_DMA_MINALIGN is greater than header size 296 */ 297 if (new_buf > buf) { 298 debug("%s: Aligned buffer is after buffer start\n", 299 __func__); 300 new_buf -= ARCH_DMA_MINALIGN; 301 } 302 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, 303 (u32)buf, (u32)new_buf, swap); 304 305 for (i = 0; i < (len/4); i++) 306 new_buf[i] = load_word(&buf[i], swap); 307 308 buf = new_buf; 309 } else if (swap != SWAP_DONE) { 310 /* For bitstream which are aligned */ 311 u32 *new_buf = (u32 *)buf; 312 313 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, 314 swap); 315 316 for (i = 0; i < (len/4); i++) 317 new_buf[i] = load_word(&buf[i], swap); 318 } 319 320 return buf; 321 } 322 323 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, 324 size_t bsize, u32 blocksize, u32 *swap, 325 u32 *partialbit) 326 { 327 u32 *buf_start; 328 u32 diff; 329 330 /* Detect if we are going working with partial or full bitstream */ 331 if (bsize != desc->size) { 332 printf("%s: Working with partial bitstream\n", __func__); 333 *partialbit = 1; 334 } 335 buf_start = check_data((u8 *)buf, blocksize, swap); 336 337 if (!buf_start) 338 return FPGA_FAIL; 339 340 /* Check if data is postpone from start */ 341 diff = (u32)buf_start - (u32)buf; 342 if (diff) { 343 printf("%s: Bitstream is not validated yet (diff %x)\n", 344 __func__, diff); 345 return FPGA_FAIL; 346 } 347 348 if ((u32)buf < SZ_1M) { 349 printf("%s: Bitstream has to be placed up to 1MB (%x)\n", 350 __func__, (u32)buf); 351 return FPGA_FAIL; 352 } 353 354 if (zynq_dma_xfer_init(*partialbit)) 355 return FPGA_FAIL; 356 357 return 0; 358 } 359 360 361 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) 362 { 363 unsigned long ts; /* Timestamp */ 364 u32 partialbit = 0; 365 u32 isr_status, swap; 366 367 /* 368 * send bsize inplace of blocksize as it was not a bitstream 369 * in chunks 370 */ 371 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, 372 &partialbit)) 373 return FPGA_FAIL; 374 375 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); 376 377 debug("%s: Source = 0x%08X\n", __func__, (u32)buf); 378 debug("%s: Size = %zu\n", __func__, bsize); 379 380 /* flush(clean & invalidate) d-cache range buf */ 381 flush_dcache_range((u32)buf, (u32)buf + 382 roundup(bsize, ARCH_DMA_MINALIGN)); 383 384 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) 385 return FPGA_FAIL; 386 387 isr_status = readl(&devcfg_base->int_sts); 388 /* Check FPGA configuration completion */ 389 ts = get_timer(0); 390 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { 391 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 392 printf("%s: Timeout wait for FPGA to config\n", 393 __func__); 394 return FPGA_FAIL; 395 } 396 isr_status = readl(&devcfg_base->int_sts); 397 } 398 399 debug("%s: FPGA config done\n", __func__); 400 401 if (!partialbit) 402 zynq_slcr_devcfg_enable(); 403 404 return FPGA_SUCCESS; 405 } 406 407 static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) 408 { 409 return FPGA_FAIL; 410 } 411 412 struct xilinx_fpga_op zynq_op = { 413 .load = zynq_load, 414 .dump = zynq_dump, 415 .info = zynq_info, 416 }; 417