xref: /openbmc/u-boot/drivers/fpga/zynqpl.c (revision 3ade5bc4)
1 /*
2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
3  *
4  * (C) Copyright 2012
5  * Joe Hershberger <joe.hershberger@ni.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <console.h>
12 #include <asm/io.h>
13 #include <fs.h>
14 #include <zynqpl.h>
15 #include <linux/sizes.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/sys_proto.h>
18 
19 #define DEVCFG_CTRL_PCFG_PROG_B		0x40000000
20 #define DEVCFG_ISR_FATAL_ERROR_MASK	0x00740040
21 #define DEVCFG_ISR_ERROR_FLAGS_MASK	0x00340840
22 #define DEVCFG_ISR_RX_FIFO_OV		0x00040000
23 #define DEVCFG_ISR_DMA_DONE		0x00002000
24 #define DEVCFG_ISR_PCFG_DONE		0x00000004
25 #define DEVCFG_STATUS_DMA_CMD_Q_F	0x80000000
26 #define DEVCFG_STATUS_DMA_CMD_Q_E	0x40000000
27 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK	0x30000000
28 #define DEVCFG_STATUS_PCFG_INIT		0x00000010
29 #define DEVCFG_MCTRL_PCAP_LPBK		0x00000010
30 #define DEVCFG_MCTRL_RFIFO_FLUSH	0x00000002
31 #define DEVCFG_MCTRL_WFIFO_FLUSH	0x00000001
32 
33 #ifndef CONFIG_SYS_FPGA_WAIT
34 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
35 #endif
36 
37 #ifndef CONFIG_SYS_FPGA_PROG_TIME
38 #define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
39 #endif
40 
41 static int zynq_info(xilinx_desc *desc)
42 {
43 	return FPGA_SUCCESS;
44 }
45 
46 #define DUMMY_WORD	0xffffffff
47 
48 /* Xilinx binary format header */
49 static const u32 bin_format[] = {
50 	DUMMY_WORD, /* Dummy words */
51 	DUMMY_WORD,
52 	DUMMY_WORD,
53 	DUMMY_WORD,
54 	DUMMY_WORD,
55 	DUMMY_WORD,
56 	DUMMY_WORD,
57 	DUMMY_WORD,
58 	0x000000bb, /* Sync word */
59 	0x11220044, /* Sync word */
60 	DUMMY_WORD,
61 	DUMMY_WORD,
62 	0xaa995566, /* Sync word */
63 };
64 
65 #define SWAP_NO		1
66 #define SWAP_DONE	2
67 
68 /*
69  * Load the whole word from unaligned buffer
70  * Keep in your mind that it is byte loading on little-endian system
71  */
72 static u32 load_word(const void *buf, u32 swap)
73 {
74 	u32 word = 0;
75 	u8 *bitc = (u8 *)buf;
76 	int p;
77 
78 	if (swap == SWAP_NO) {
79 		for (p = 0; p < 4; p++) {
80 			word <<= 8;
81 			word |= bitc[p];
82 		}
83 	} else {
84 		for (p = 3; p >= 0; p--) {
85 			word <<= 8;
86 			word |= bitc[p];
87 		}
88 	}
89 
90 	return word;
91 }
92 
93 static u32 check_header(const void *buf)
94 {
95 	u32 i, pattern;
96 	int swap = SWAP_NO;
97 	u32 *test = (u32 *)buf;
98 
99 	debug("%s: Let's check bitstream header\n", __func__);
100 
101 	/* Checking that passing bin is not a bitstream */
102 	for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
103 		pattern = load_word(&test[i], swap);
104 
105 		/*
106 		 * Bitstreams in binary format are swapped
107 		 * compare to regular bistream.
108 		 * Do not swap dummy word but if swap is done assume
109 		 * that parsing buffer is binary format
110 		 */
111 		if ((__swab32(pattern) != DUMMY_WORD) &&
112 		    (__swab32(pattern) == bin_format[i])) {
113 			pattern = __swab32(pattern);
114 			swap = SWAP_DONE;
115 			debug("%s: data swapped - let's swap\n", __func__);
116 		}
117 
118 		debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
119 		      (u32)&test[i], pattern, bin_format[i]);
120 		if (pattern != bin_format[i]) {
121 			debug("%s: Bitstream is not recognized\n", __func__);
122 			return 0;
123 		}
124 	}
125 	debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
126 	      (u32)buf, swap == SWAP_NO ? "without" : "with");
127 
128 	return swap;
129 }
130 
131 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
132 {
133 	u32 word, p = 0; /* possition */
134 
135 	/* Because buf doesn't need to be aligned let's read it by chars */
136 	for (p = 0; p < bsize; p++) {
137 		word = load_word(&buf[p], SWAP_NO);
138 		debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
139 
140 		/* Find the first bitstream dummy word */
141 		if (word == DUMMY_WORD) {
142 			debug("%s: Found dummy word at position %x/%x\n",
143 			      __func__, p, (u32)&buf[p]);
144 			*swap = check_header(&buf[p]);
145 			if (*swap) {
146 				/* FIXME add full bitstream checking here */
147 				return &buf[p];
148 			}
149 		}
150 		/* Loop can be huge - support CTRL + C */
151 		if (ctrlc())
152 			return NULL;
153 	}
154 	return NULL;
155 }
156 
157 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
158 {
159 	unsigned long ts;
160 	u32 isr_status;
161 
162 	/* Set up the transfer */
163 	writel((u32)srcbuf, &devcfg_base->dma_src_addr);
164 	writel(dstbuf, &devcfg_base->dma_dst_addr);
165 	writel(srclen, &devcfg_base->dma_src_len);
166 	writel(dstlen, &devcfg_base->dma_dst_len);
167 
168 	isr_status = readl(&devcfg_base->int_sts);
169 
170 	/* Polling the PCAP_INIT status for Set */
171 	ts = get_timer(0);
172 	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
173 		if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
174 			debug("%s: Error: isr = 0x%08X\n", __func__,
175 			      isr_status);
176 			debug("%s: Write count = 0x%08X\n", __func__,
177 			      readl(&devcfg_base->write_count));
178 			debug("%s: Read count = 0x%08X\n", __func__,
179 			      readl(&devcfg_base->read_count));
180 
181 			return FPGA_FAIL;
182 		}
183 		if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
184 			printf("%s: Timeout wait for DMA to complete\n",
185 			       __func__);
186 			return FPGA_FAIL;
187 		}
188 		isr_status = readl(&devcfg_base->int_sts);
189 	}
190 
191 	debug("%s: DMA transfer is done\n", __func__);
192 
193 	/* Clear out the DMA status */
194 	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
195 
196 	return FPGA_SUCCESS;
197 }
198 
199 static int zynq_dma_xfer_init(bitstream_type bstype)
200 {
201 	u32 status, control, isr_status;
202 	unsigned long ts;
203 
204 	/* Clear loopback bit */
205 	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
206 
207 	if (bstype != BIT_PARTIAL) {
208 		zynq_slcr_devcfg_disable();
209 
210 		/* Setting PCFG_PROG_B signal to high */
211 		control = readl(&devcfg_base->ctrl);
212 		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
213 		/* Setting PCFG_PROG_B signal to low */
214 		writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
215 
216 		/* Polling the PCAP_INIT status for Reset */
217 		ts = get_timer(0);
218 		while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
219 			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
220 				printf("%s: Timeout wait for INIT to clear\n",
221 				       __func__);
222 				return FPGA_FAIL;
223 			}
224 		}
225 
226 		/* Setting PCFG_PROG_B signal to high */
227 		writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
228 
229 		/* Polling the PCAP_INIT status for Set */
230 		ts = get_timer(0);
231 		while (!(readl(&devcfg_base->status) &
232 			DEVCFG_STATUS_PCFG_INIT)) {
233 			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
234 				printf("%s: Timeout wait for INIT to set\n",
235 				       __func__);
236 				return FPGA_FAIL;
237 			}
238 		}
239 	}
240 
241 	isr_status = readl(&devcfg_base->int_sts);
242 
243 	/* Clear it all, so if Boot ROM comes back, it can proceed */
244 	writel(0xFFFFFFFF, &devcfg_base->int_sts);
245 
246 	if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
247 		debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
248 
249 		/* If RX FIFO overflow, need to flush RX FIFO first */
250 		if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
251 			writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
252 			writel(0xFFFFFFFF, &devcfg_base->int_sts);
253 		}
254 		return FPGA_FAIL;
255 	}
256 
257 	status = readl(&devcfg_base->status);
258 
259 	debug("%s: Status = 0x%08X\n", __func__, status);
260 
261 	if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
262 		debug("%s: Error: device busy\n", __func__);
263 		return FPGA_FAIL;
264 	}
265 
266 	debug("%s: Device ready\n", __func__);
267 
268 	if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
269 		if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
270 			/* Error state, transfer cannot occur */
271 			debug("%s: ISR indicates error\n", __func__);
272 			return FPGA_FAIL;
273 		} else {
274 			/* Clear out the status */
275 			writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
276 		}
277 	}
278 
279 	if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
280 		/* Clear the count of completed DMA transfers */
281 		writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
282 	}
283 
284 	return FPGA_SUCCESS;
285 }
286 
287 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
288 {
289 	u32 *new_buf;
290 	u32 i;
291 
292 	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
293 		new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
294 
295 		/*
296 		 * This might be dangerous but permits to flash if
297 		 * ARCH_DMA_MINALIGN is greater than header size
298 		 */
299 		if (new_buf > buf) {
300 			debug("%s: Aligned buffer is after buffer start\n",
301 			      __func__);
302 			new_buf -= ARCH_DMA_MINALIGN;
303 		}
304 		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
305 		       (u32)buf, (u32)new_buf, swap);
306 
307 		for (i = 0; i < (len/4); i++)
308 			new_buf[i] = load_word(&buf[i], swap);
309 
310 		buf = new_buf;
311 	} else if (swap != SWAP_DONE) {
312 		/* For bitstream which are aligned */
313 		u32 *new_buf = (u32 *)buf;
314 
315 		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
316 		       swap);
317 
318 		for (i = 0; i < (len/4); i++)
319 			new_buf[i] = load_word(&buf[i], swap);
320 	}
321 
322 	return buf;
323 }
324 
325 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
326 				   size_t bsize, u32 blocksize, u32 *swap,
327 				   bitstream_type *bstype)
328 {
329 	u32 *buf_start;
330 	u32 diff;
331 
332 	buf_start = check_data((u8 *)buf, blocksize, swap);
333 
334 	if (!buf_start)
335 		return FPGA_FAIL;
336 
337 	/* Check if data is postpone from start */
338 	diff = (u32)buf_start - (u32)buf;
339 	if (diff) {
340 		printf("%s: Bitstream is not validated yet (diff %x)\n",
341 		       __func__, diff);
342 		return FPGA_FAIL;
343 	}
344 
345 	if ((u32)buf < SZ_1M) {
346 		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
347 		       __func__, (u32)buf);
348 		return FPGA_FAIL;
349 	}
350 
351 	if (zynq_dma_xfer_init(*bstype))
352 		return FPGA_FAIL;
353 
354 	return 0;
355 }
356 
357 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
358 		     bitstream_type bstype)
359 {
360 	unsigned long ts; /* Timestamp */
361 	u32 isr_status, swap;
362 
363 	/*
364 	 * send bsize inplace of blocksize as it was not a bitstream
365 	 * in chunks
366 	 */
367 	if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
368 				    &bstype))
369 		return FPGA_FAIL;
370 
371 	buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
372 
373 	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
374 	debug("%s: Size = %zu\n", __func__, bsize);
375 
376 	/* flush(clean & invalidate) d-cache range buf */
377 	flush_dcache_range((u32)buf, (u32)buf +
378 			   roundup(bsize, ARCH_DMA_MINALIGN));
379 
380 	if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
381 		return FPGA_FAIL;
382 
383 	isr_status = readl(&devcfg_base->int_sts);
384 	/* Check FPGA configuration completion */
385 	ts = get_timer(0);
386 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
387 		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
388 			printf("%s: Timeout wait for FPGA to config\n",
389 			       __func__);
390 			return FPGA_FAIL;
391 		}
392 		isr_status = readl(&devcfg_base->int_sts);
393 	}
394 
395 	debug("%s: FPGA config done\n", __func__);
396 
397 	if (bstype != BIT_PARTIAL)
398 		zynq_slcr_devcfg_enable();
399 
400 	return FPGA_SUCCESS;
401 }
402 
403 #if defined(CONFIG_CMD_FPGA_LOADFS)
404 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
405 		       fpga_fs_info *fsinfo)
406 {
407 	unsigned long ts; /* Timestamp */
408 	u32 isr_status, swap;
409 	u32 partialbit = 0;
410 	loff_t blocksize, actread;
411 	loff_t pos = 0;
412 	int fstype;
413 	char *interface, *dev_part, *filename;
414 
415 	blocksize = fsinfo->blocksize;
416 	interface = fsinfo->interface;
417 	dev_part = fsinfo->dev_part;
418 	filename = fsinfo->filename;
419 	fstype = fsinfo->fstype;
420 
421 	if (fs_set_blk_dev(interface, dev_part, fstype))
422 		return FPGA_FAIL;
423 
424 	if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
425 		return FPGA_FAIL;
426 
427 	if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
428 				    &partialbit))
429 		return FPGA_FAIL;
430 
431 	dcache_disable();
432 
433 	do {
434 		buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
435 
436 		if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
437 				      0xffffffff, 0))
438 			return FPGA_FAIL;
439 
440 		bsize -= blocksize;
441 		pos   += blocksize;
442 
443 		if (fs_set_blk_dev(interface, dev_part, fstype))
444 			return FPGA_FAIL;
445 
446 		if (bsize > blocksize) {
447 			if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
448 				return FPGA_FAIL;
449 		} else {
450 			if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
451 				return FPGA_FAIL;
452 		}
453 	} while (bsize > blocksize);
454 
455 	buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
456 
457 	if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
458 		return FPGA_FAIL;
459 
460 	dcache_enable();
461 
462 	isr_status = readl(&devcfg_base->int_sts);
463 
464 	/* Check FPGA configuration completion */
465 	ts = get_timer(0);
466 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
467 		if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
468 			printf("%s: Timeout wait for FPGA to config\n",
469 			       __func__);
470 			return FPGA_FAIL;
471 		}
472 		isr_status = readl(&devcfg_base->int_sts);
473 	}
474 
475 	debug("%s: FPGA config done\n", __func__);
476 
477 	if (!partialbit)
478 		zynq_slcr_devcfg_enable();
479 
480 	return FPGA_SUCCESS;
481 }
482 #endif
483 
484 static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
485 {
486 	return FPGA_FAIL;
487 }
488 
489 struct xilinx_fpga_op zynq_op = {
490 	.load = zynq_load,
491 #if defined(CONFIG_CMD_FPGA_LOADFS)
492 	.loadfs = zynq_loadfs,
493 #endif
494 	.dump = zynq_dump,
495 	.info = zynq_info,
496 };
497