1 /* 2 * (C) Copyright 2012-2013, Xilinx, Michal Simek 3 * 4 * (C) Copyright 2012 5 * Joe Hershberger <joe.hershberger@ni.com> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <asm/io.h> 28 #include <zynqpl.h> 29 #include <asm/arch/hardware.h> 30 #include <asm/arch/sys_proto.h> 31 32 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 33 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 34 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 35 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 36 #define DEVCFG_ISR_DMA_DONE 0x00002000 37 #define DEVCFG_ISR_PCFG_DONE 0x00000004 38 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 39 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 40 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 41 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 42 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 43 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 44 45 #ifndef CONFIG_SYS_FPGA_WAIT 46 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ 47 #endif 48 49 #ifndef CONFIG_SYS_FPGA_PROG_TIME 50 #define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ 51 #endif 52 53 int zynq_info(Xilinx_desc *desc) 54 { 55 return FPGA_SUCCESS; 56 } 57 58 #define DUMMY_WORD 0xffffffff 59 60 /* Xilinx binary format header */ 61 static const u32 bin_format[] = { 62 DUMMY_WORD, /* Dummy words */ 63 DUMMY_WORD, 64 DUMMY_WORD, 65 DUMMY_WORD, 66 DUMMY_WORD, 67 DUMMY_WORD, 68 DUMMY_WORD, 69 DUMMY_WORD, 70 0x000000bb, /* Sync word */ 71 0x11220044, /* Sync word */ 72 DUMMY_WORD, 73 DUMMY_WORD, 74 0xaa995566, /* Sync word */ 75 }; 76 77 #define SWAP_NO 1 78 #define SWAP_DONE 2 79 80 /* 81 * Load the whole word from unaligned buffer 82 * Keep in your mind that it is byte loading on little-endian system 83 */ 84 static u32 load_word(const void *buf, u32 swap) 85 { 86 u32 word = 0; 87 u8 *bitc = (u8 *)buf; 88 int p; 89 90 if (swap == SWAP_NO) { 91 for (p = 0; p < 4; p++) { 92 word <<= 8; 93 word |= bitc[p]; 94 } 95 } else { 96 for (p = 3; p >= 0; p--) { 97 word <<= 8; 98 word |= bitc[p]; 99 } 100 } 101 102 return word; 103 } 104 105 static u32 check_header(const void *buf) 106 { 107 u32 i, pattern; 108 int swap = SWAP_NO; 109 u32 *test = (u32 *)buf; 110 111 debug("%s: Let's check bitstream header\n", __func__); 112 113 /* Checking that passing bin is not a bitstream */ 114 for (i = 0; i < ARRAY_SIZE(bin_format); i++) { 115 pattern = load_word(&test[i], swap); 116 117 /* 118 * Bitstreams in binary format are swapped 119 * compare to regular bistream. 120 * Do not swap dummy word but if swap is done assume 121 * that parsing buffer is binary format 122 */ 123 if ((__swab32(pattern) != DUMMY_WORD) && 124 (__swab32(pattern) == bin_format[i])) { 125 pattern = __swab32(pattern); 126 swap = SWAP_DONE; 127 debug("%s: data swapped - let's swap\n", __func__); 128 } 129 130 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, 131 (u32)&test[i], pattern, bin_format[i]); 132 if (pattern != bin_format[i]) { 133 debug("%s: Bitstream is not recognized\n", __func__); 134 return 0; 135 } 136 } 137 debug("%s: Found bitstream header at %x %s swapinng\n", __func__, 138 (u32)buf, swap == SWAP_NO ? "without" : "with"); 139 140 return swap; 141 } 142 143 static void *check_data(u8 *buf, size_t bsize, u32 *swap) 144 { 145 u32 word, p = 0; /* possition */ 146 147 /* Because buf doesn't need to be aligned let's read it by chars */ 148 for (p = 0; p < bsize; p++) { 149 word = load_word(&buf[p], SWAP_NO); 150 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); 151 152 /* Find the first bitstream dummy word */ 153 if (word == DUMMY_WORD) { 154 debug("%s: Found dummy word at position %x/%x\n", 155 __func__, p, (u32)&buf[p]); 156 *swap = check_header(&buf[p]); 157 if (*swap) { 158 /* FIXME add full bitstream checking here */ 159 return &buf[p]; 160 } 161 } 162 /* Loop can be huge - support CTRL + C */ 163 if (ctrlc()) 164 return 0; 165 } 166 return 0; 167 } 168 169 170 int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) 171 { 172 unsigned long ts; /* Timestamp */ 173 u32 partialbit = 0; 174 u32 i, control, isr_status, status, swap, diff; 175 u32 *buf_start; 176 177 /* Detect if we are going working with partial or full bitstream */ 178 if (bsize != desc->size) { 179 printf("%s: Working with partial bitstream\n", __func__); 180 partialbit = 1; 181 } 182 183 buf_start = check_data((u8 *)buf, bsize, &swap); 184 if (!buf_start) 185 return FPGA_FAIL; 186 187 /* Check if data is postpone from start */ 188 diff = (u32)buf_start - (u32)buf; 189 if (diff) { 190 printf("%s: Bitstream is not validated yet (diff %x)\n", 191 __func__, diff); 192 return FPGA_FAIL; 193 } 194 195 if ((u32)buf_start & 0x3) { 196 u32 *new_buf = (u32 *)((u32)buf & ~0x3); 197 198 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, 199 (u32)buf_start, (u32)new_buf, swap); 200 201 for (i = 0; i < (bsize/4); i++) 202 new_buf[i] = load_word(&buf_start[i], swap); 203 204 swap = SWAP_DONE; 205 buf = new_buf; 206 } else if (swap != SWAP_DONE) { 207 /* For bitstream which are aligned */ 208 u32 *new_buf = (u32 *)buf; 209 210 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, 211 swap); 212 213 for (i = 0; i < (bsize/4); i++) 214 new_buf[i] = load_word(&buf_start[i], swap); 215 216 swap = SWAP_DONE; 217 } 218 219 if (!partialbit) { 220 zynq_slcr_devcfg_disable(); 221 222 /* Setting PCFG_PROG_B signal to high */ 223 control = readl(&devcfg_base->ctrl); 224 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 225 /* Setting PCFG_PROG_B signal to low */ 226 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 227 228 /* Polling the PCAP_INIT status for Reset */ 229 ts = get_timer(0); 230 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { 231 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 232 printf("%s: Timeout wait for INIT to clear\n", 233 __func__); 234 return FPGA_FAIL; 235 } 236 } 237 238 /* Setting PCFG_PROG_B signal to high */ 239 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 240 241 /* Polling the PCAP_INIT status for Set */ 242 ts = get_timer(0); 243 while (!(readl(&devcfg_base->status) & 244 DEVCFG_STATUS_PCFG_INIT)) { 245 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 246 printf("%s: Timeout wait for INIT to set\n", 247 __func__); 248 return FPGA_FAIL; 249 } 250 } 251 } 252 253 isr_status = readl(&devcfg_base->int_sts); 254 255 /* Clear it all, so if Boot ROM comes back, it can proceed */ 256 writel(0xFFFFFFFF, &devcfg_base->int_sts); 257 258 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { 259 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); 260 261 /* If RX FIFO overflow, need to flush RX FIFO first */ 262 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { 263 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); 264 writel(0xFFFFFFFF, &devcfg_base->int_sts); 265 } 266 return FPGA_FAIL; 267 } 268 269 status = readl(&devcfg_base->status); 270 271 debug("%s: Status = 0x%08X\n", __func__, status); 272 273 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { 274 debug("%s: Error: device busy\n", __func__); 275 return FPGA_FAIL; 276 } 277 278 debug("%s: Device ready\n", __func__); 279 280 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { 281 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { 282 /* Error state, transfer cannot occur */ 283 debug("%s: ISR indicates error\n", __func__); 284 return FPGA_FAIL; 285 } else { 286 /* Clear out the status */ 287 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 288 } 289 } 290 291 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { 292 /* Clear the count of completed DMA transfers */ 293 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); 294 } 295 296 debug("%s: Source = 0x%08X\n", __func__, (u32)buf); 297 debug("%s: Size = %zu\n", __func__, bsize); 298 299 /* Set up the transfer */ 300 writel((u32)buf | 1, &devcfg_base->dma_src_addr); 301 writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); 302 writel(bsize >> 2, &devcfg_base->dma_src_len); 303 writel(0, &devcfg_base->dma_dst_len); 304 305 isr_status = readl(&devcfg_base->int_sts); 306 307 /* Polling the PCAP_INIT status for Set */ 308 ts = get_timer(0); 309 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { 310 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { 311 debug("%s: Error: isr = 0x%08X\n", __func__, 312 isr_status); 313 debug("%s: Write count = 0x%08X\n", __func__, 314 readl(&devcfg_base->write_count)); 315 debug("%s: Read count = 0x%08X\n", __func__, 316 readl(&devcfg_base->read_count)); 317 318 return FPGA_FAIL; 319 } 320 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { 321 printf("%s: Timeout wait for DMA to complete\n", 322 __func__); 323 return FPGA_FAIL; 324 } 325 isr_status = readl(&devcfg_base->int_sts); 326 } 327 328 debug("%s: DMA transfer is done\n", __func__); 329 330 /* Check FPGA configuration completion */ 331 ts = get_timer(0); 332 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { 333 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 334 printf("%s: Timeout wait for FPGA to config\n", 335 __func__); 336 return FPGA_FAIL; 337 } 338 isr_status = readl(&devcfg_base->int_sts); 339 } 340 341 debug("%s: FPGA config done\n", __func__); 342 343 /* Clear out the DMA status */ 344 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 345 346 if (!partialbit) 347 zynq_slcr_devcfg_enable(); 348 349 return FPGA_SUCCESS; 350 } 351 352 int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) 353 { 354 return FPGA_FAIL; 355 } 356