1 /* 2 * (C) Copyright 2012-2013, Xilinx, Michal Simek 3 * 4 * (C) Copyright 2012 5 * Joe Hershberger <joe.hershberger@ni.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <zynqpl.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/sys_proto.h> 15 16 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 17 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 18 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 19 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 20 #define DEVCFG_ISR_DMA_DONE 0x00002000 21 #define DEVCFG_ISR_PCFG_DONE 0x00000004 22 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 23 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 24 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 25 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 26 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 27 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 28 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 29 30 #ifndef CONFIG_SYS_FPGA_WAIT 31 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ 32 #endif 33 34 #ifndef CONFIG_SYS_FPGA_PROG_TIME 35 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ 36 #endif 37 38 int zynq_info(Xilinx_desc *desc) 39 { 40 return FPGA_SUCCESS; 41 } 42 43 #define DUMMY_WORD 0xffffffff 44 45 /* Xilinx binary format header */ 46 static const u32 bin_format[] = { 47 DUMMY_WORD, /* Dummy words */ 48 DUMMY_WORD, 49 DUMMY_WORD, 50 DUMMY_WORD, 51 DUMMY_WORD, 52 DUMMY_WORD, 53 DUMMY_WORD, 54 DUMMY_WORD, 55 0x000000bb, /* Sync word */ 56 0x11220044, /* Sync word */ 57 DUMMY_WORD, 58 DUMMY_WORD, 59 0xaa995566, /* Sync word */ 60 }; 61 62 #define SWAP_NO 1 63 #define SWAP_DONE 2 64 65 /* 66 * Load the whole word from unaligned buffer 67 * Keep in your mind that it is byte loading on little-endian system 68 */ 69 static u32 load_word(const void *buf, u32 swap) 70 { 71 u32 word = 0; 72 u8 *bitc = (u8 *)buf; 73 int p; 74 75 if (swap == SWAP_NO) { 76 for (p = 0; p < 4; p++) { 77 word <<= 8; 78 word |= bitc[p]; 79 } 80 } else { 81 for (p = 3; p >= 0; p--) { 82 word <<= 8; 83 word |= bitc[p]; 84 } 85 } 86 87 return word; 88 } 89 90 static u32 check_header(const void *buf) 91 { 92 u32 i, pattern; 93 int swap = SWAP_NO; 94 u32 *test = (u32 *)buf; 95 96 debug("%s: Let's check bitstream header\n", __func__); 97 98 /* Checking that passing bin is not a bitstream */ 99 for (i = 0; i < ARRAY_SIZE(bin_format); i++) { 100 pattern = load_word(&test[i], swap); 101 102 /* 103 * Bitstreams in binary format are swapped 104 * compare to regular bistream. 105 * Do not swap dummy word but if swap is done assume 106 * that parsing buffer is binary format 107 */ 108 if ((__swab32(pattern) != DUMMY_WORD) && 109 (__swab32(pattern) == bin_format[i])) { 110 pattern = __swab32(pattern); 111 swap = SWAP_DONE; 112 debug("%s: data swapped - let's swap\n", __func__); 113 } 114 115 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, 116 (u32)&test[i], pattern, bin_format[i]); 117 if (pattern != bin_format[i]) { 118 debug("%s: Bitstream is not recognized\n", __func__); 119 return 0; 120 } 121 } 122 debug("%s: Found bitstream header at %x %s swapinng\n", __func__, 123 (u32)buf, swap == SWAP_NO ? "without" : "with"); 124 125 return swap; 126 } 127 128 static void *check_data(u8 *buf, size_t bsize, u32 *swap) 129 { 130 u32 word, p = 0; /* possition */ 131 132 /* Because buf doesn't need to be aligned let's read it by chars */ 133 for (p = 0; p < bsize; p++) { 134 word = load_word(&buf[p], SWAP_NO); 135 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); 136 137 /* Find the first bitstream dummy word */ 138 if (word == DUMMY_WORD) { 139 debug("%s: Found dummy word at position %x/%x\n", 140 __func__, p, (u32)&buf[p]); 141 *swap = check_header(&buf[p]); 142 if (*swap) { 143 /* FIXME add full bitstream checking here */ 144 return &buf[p]; 145 } 146 } 147 /* Loop can be huge - support CTRL + C */ 148 if (ctrlc()) 149 return 0; 150 } 151 return 0; 152 } 153 154 155 int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) 156 { 157 unsigned long ts; /* Timestamp */ 158 u32 partialbit = 0; 159 u32 i, control, isr_status, status, swap, diff; 160 u32 *buf_start; 161 162 /* Detect if we are going working with partial or full bitstream */ 163 if (bsize != desc->size) { 164 printf("%s: Working with partial bitstream\n", __func__); 165 partialbit = 1; 166 } 167 168 buf_start = check_data((u8 *)buf, bsize, &swap); 169 if (!buf_start) 170 return FPGA_FAIL; 171 172 /* Check if data is postpone from start */ 173 diff = (u32)buf_start - (u32)buf; 174 if (diff) { 175 printf("%s: Bitstream is not validated yet (diff %x)\n", 176 __func__, diff); 177 return FPGA_FAIL; 178 } 179 180 if ((u32)buf_start & 0x3) { 181 u32 *new_buf = (u32 *)((u32)buf & ~0x3); 182 183 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, 184 (u32)buf_start, (u32)new_buf, swap); 185 186 for (i = 0; i < (bsize/4); i++) 187 new_buf[i] = load_word(&buf_start[i], swap); 188 189 swap = SWAP_DONE; 190 buf = new_buf; 191 } else if (swap != SWAP_DONE) { 192 /* For bitstream which are aligned */ 193 u32 *new_buf = (u32 *)buf; 194 195 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, 196 swap); 197 198 for (i = 0; i < (bsize/4); i++) 199 new_buf[i] = load_word(&buf_start[i], swap); 200 201 swap = SWAP_DONE; 202 } 203 204 /* Clear loopback bit */ 205 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); 206 207 if (!partialbit) { 208 zynq_slcr_devcfg_disable(); 209 210 /* Setting PCFG_PROG_B signal to high */ 211 control = readl(&devcfg_base->ctrl); 212 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 213 /* Setting PCFG_PROG_B signal to low */ 214 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 215 216 /* Polling the PCAP_INIT status for Reset */ 217 ts = get_timer(0); 218 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { 219 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 220 printf("%s: Timeout wait for INIT to clear\n", 221 __func__); 222 return FPGA_FAIL; 223 } 224 } 225 226 /* Setting PCFG_PROG_B signal to high */ 227 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 228 229 /* Polling the PCAP_INIT status for Set */ 230 ts = get_timer(0); 231 while (!(readl(&devcfg_base->status) & 232 DEVCFG_STATUS_PCFG_INIT)) { 233 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 234 printf("%s: Timeout wait for INIT to set\n", 235 __func__); 236 return FPGA_FAIL; 237 } 238 } 239 } 240 241 isr_status = readl(&devcfg_base->int_sts); 242 243 /* Clear it all, so if Boot ROM comes back, it can proceed */ 244 writel(0xFFFFFFFF, &devcfg_base->int_sts); 245 246 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { 247 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); 248 249 /* If RX FIFO overflow, need to flush RX FIFO first */ 250 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { 251 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); 252 writel(0xFFFFFFFF, &devcfg_base->int_sts); 253 } 254 return FPGA_FAIL; 255 } 256 257 status = readl(&devcfg_base->status); 258 259 debug("%s: Status = 0x%08X\n", __func__, status); 260 261 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { 262 debug("%s: Error: device busy\n", __func__); 263 return FPGA_FAIL; 264 } 265 266 debug("%s: Device ready\n", __func__); 267 268 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { 269 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { 270 /* Error state, transfer cannot occur */ 271 debug("%s: ISR indicates error\n", __func__); 272 return FPGA_FAIL; 273 } else { 274 /* Clear out the status */ 275 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 276 } 277 } 278 279 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { 280 /* Clear the count of completed DMA transfers */ 281 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); 282 } 283 284 debug("%s: Source = 0x%08X\n", __func__, (u32)buf); 285 debug("%s: Size = %zu\n", __func__, bsize); 286 287 /* Set up the transfer */ 288 writel((u32)buf | 1, &devcfg_base->dma_src_addr); 289 writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); 290 writel(bsize >> 2, &devcfg_base->dma_src_len); 291 writel(0, &devcfg_base->dma_dst_len); 292 293 isr_status = readl(&devcfg_base->int_sts); 294 295 /* Polling the PCAP_INIT status for Set */ 296 ts = get_timer(0); 297 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { 298 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { 299 debug("%s: Error: isr = 0x%08X\n", __func__, 300 isr_status); 301 debug("%s: Write count = 0x%08X\n", __func__, 302 readl(&devcfg_base->write_count)); 303 debug("%s: Read count = 0x%08X\n", __func__, 304 readl(&devcfg_base->read_count)); 305 306 return FPGA_FAIL; 307 } 308 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { 309 printf("%s: Timeout wait for DMA to complete\n", 310 __func__); 311 return FPGA_FAIL; 312 } 313 isr_status = readl(&devcfg_base->int_sts); 314 } 315 316 debug("%s: DMA transfer is done\n", __func__); 317 318 /* Check FPGA configuration completion */ 319 ts = get_timer(0); 320 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { 321 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 322 printf("%s: Timeout wait for FPGA to config\n", 323 __func__); 324 return FPGA_FAIL; 325 } 326 isr_status = readl(&devcfg_base->int_sts); 327 } 328 329 debug("%s: FPGA config done\n", __func__); 330 331 /* Clear out the DMA status */ 332 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 333 334 if (!partialbit) 335 zynq_slcr_devcfg_enable(); 336 337 return FPGA_SUCCESS; 338 } 339 340 int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) 341 { 342 return FPGA_FAIL; 343 } 344