1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
5 * (C) Copyright 2012
6 * Joe Hershberger <joe.hershberger@ni.com>
7 */
8
9 #include <common.h>
10 #include <console.h>
11 #include <asm/io.h>
12 #include <fs.h>
13 #include <zynqpl.h>
14 #include <linux/sizes.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17
18 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
19 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
20 #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
21 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
22 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
23 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
24 #define DEVCFG_ISR_DMA_DONE 0x00002000
25 #define DEVCFG_ISR_PCFG_DONE 0x00000004
26 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
27 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
28 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
29 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
30 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
31 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
32 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
33
34 #ifndef CONFIG_SYS_FPGA_WAIT
35 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
36 #endif
37
38 #ifndef CONFIG_SYS_FPGA_PROG_TIME
39 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
40 #endif
41
42 #define DUMMY_WORD 0xffffffff
43
44 /* Xilinx binary format header */
45 static const u32 bin_format[] = {
46 DUMMY_WORD, /* Dummy words */
47 DUMMY_WORD,
48 DUMMY_WORD,
49 DUMMY_WORD,
50 DUMMY_WORD,
51 DUMMY_WORD,
52 DUMMY_WORD,
53 DUMMY_WORD,
54 0x000000bb, /* Sync word */
55 0x11220044, /* Sync word */
56 DUMMY_WORD,
57 DUMMY_WORD,
58 0xaa995566, /* Sync word */
59 };
60
61 #define SWAP_NO 1
62 #define SWAP_DONE 2
63
64 /*
65 * Load the whole word from unaligned buffer
66 * Keep in your mind that it is byte loading on little-endian system
67 */
load_word(const void * buf,u32 swap)68 static u32 load_word(const void *buf, u32 swap)
69 {
70 u32 word = 0;
71 u8 *bitc = (u8 *)buf;
72 int p;
73
74 if (swap == SWAP_NO) {
75 for (p = 0; p < 4; p++) {
76 word <<= 8;
77 word |= bitc[p];
78 }
79 } else {
80 for (p = 3; p >= 0; p--) {
81 word <<= 8;
82 word |= bitc[p];
83 }
84 }
85
86 return word;
87 }
88
check_header(const void * buf)89 static u32 check_header(const void *buf)
90 {
91 u32 i, pattern;
92 int swap = SWAP_NO;
93 u32 *test = (u32 *)buf;
94
95 debug("%s: Let's check bitstream header\n", __func__);
96
97 /* Checking that passing bin is not a bitstream */
98 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
99 pattern = load_word(&test[i], swap);
100
101 /*
102 * Bitstreams in binary format are swapped
103 * compare to regular bistream.
104 * Do not swap dummy word but if swap is done assume
105 * that parsing buffer is binary format
106 */
107 if ((__swab32(pattern) != DUMMY_WORD) &&
108 (__swab32(pattern) == bin_format[i])) {
109 pattern = __swab32(pattern);
110 swap = SWAP_DONE;
111 debug("%s: data swapped - let's swap\n", __func__);
112 }
113
114 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
115 (u32)&test[i], pattern, bin_format[i]);
116 if (pattern != bin_format[i]) {
117 debug("%s: Bitstream is not recognized\n", __func__);
118 return 0;
119 }
120 }
121 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
122 (u32)buf, swap == SWAP_NO ? "without" : "with");
123
124 return swap;
125 }
126
check_data(u8 * buf,size_t bsize,u32 * swap)127 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
128 {
129 u32 word, p = 0; /* possition */
130
131 /* Because buf doesn't need to be aligned let's read it by chars */
132 for (p = 0; p < bsize; p++) {
133 word = load_word(&buf[p], SWAP_NO);
134 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
135
136 /* Find the first bitstream dummy word */
137 if (word == DUMMY_WORD) {
138 debug("%s: Found dummy word at position %x/%x\n",
139 __func__, p, (u32)&buf[p]);
140 *swap = check_header(&buf[p]);
141 if (*swap) {
142 /* FIXME add full bitstream checking here */
143 return &buf[p];
144 }
145 }
146 /* Loop can be huge - support CTRL + C */
147 if (ctrlc())
148 return NULL;
149 }
150 return NULL;
151 }
152
zynq_dma_transfer(u32 srcbuf,u32 srclen,u32 dstbuf,u32 dstlen)153 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
154 {
155 unsigned long ts;
156 u32 isr_status;
157
158 /* Set up the transfer */
159 writel((u32)srcbuf, &devcfg_base->dma_src_addr);
160 writel(dstbuf, &devcfg_base->dma_dst_addr);
161 writel(srclen, &devcfg_base->dma_src_len);
162 writel(dstlen, &devcfg_base->dma_dst_len);
163
164 isr_status = readl(&devcfg_base->int_sts);
165
166 /* Polling the PCAP_INIT status for Set */
167 ts = get_timer(0);
168 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
169 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
170 debug("%s: Error: isr = 0x%08X\n", __func__,
171 isr_status);
172 debug("%s: Write count = 0x%08X\n", __func__,
173 readl(&devcfg_base->write_count));
174 debug("%s: Read count = 0x%08X\n", __func__,
175 readl(&devcfg_base->read_count));
176
177 return FPGA_FAIL;
178 }
179 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
180 printf("%s: Timeout wait for DMA to complete\n",
181 __func__);
182 return FPGA_FAIL;
183 }
184 isr_status = readl(&devcfg_base->int_sts);
185 }
186
187 debug("%s: DMA transfer is done\n", __func__);
188
189 /* Clear out the DMA status */
190 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
191
192 return FPGA_SUCCESS;
193 }
194
zynq_dma_xfer_init(bitstream_type bstype)195 static int zynq_dma_xfer_init(bitstream_type bstype)
196 {
197 u32 status, control, isr_status;
198 unsigned long ts;
199
200 /* Clear loopback bit */
201 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
202
203 if (bstype != BIT_PARTIAL) {
204 zynq_slcr_devcfg_disable();
205
206 /* Setting PCFG_PROG_B signal to high */
207 control = readl(&devcfg_base->ctrl);
208 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
209
210 /*
211 * Delay is required if AES efuse is selected as
212 * key source.
213 */
214 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
215 mdelay(5);
216
217 /* Setting PCFG_PROG_B signal to low */
218 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
219
220 /*
221 * Delay is required if AES efuse is selected as
222 * key source.
223 */
224 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
225 mdelay(5);
226
227 /* Polling the PCAP_INIT status for Reset */
228 ts = get_timer(0);
229 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
230 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
231 printf("%s: Timeout wait for INIT to clear\n",
232 __func__);
233 return FPGA_FAIL;
234 }
235 }
236
237 /* Setting PCFG_PROG_B signal to high */
238 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
239
240 /* Polling the PCAP_INIT status for Set */
241 ts = get_timer(0);
242 while (!(readl(&devcfg_base->status) &
243 DEVCFG_STATUS_PCFG_INIT)) {
244 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
245 printf("%s: Timeout wait for INIT to set\n",
246 __func__);
247 return FPGA_FAIL;
248 }
249 }
250 }
251
252 isr_status = readl(&devcfg_base->int_sts);
253
254 /* Clear it all, so if Boot ROM comes back, it can proceed */
255 writel(0xFFFFFFFF, &devcfg_base->int_sts);
256
257 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
258 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
259
260 /* If RX FIFO overflow, need to flush RX FIFO first */
261 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
262 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
263 writel(0xFFFFFFFF, &devcfg_base->int_sts);
264 }
265 return FPGA_FAIL;
266 }
267
268 status = readl(&devcfg_base->status);
269
270 debug("%s: Status = 0x%08X\n", __func__, status);
271
272 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
273 debug("%s: Error: device busy\n", __func__);
274 return FPGA_FAIL;
275 }
276
277 debug("%s: Device ready\n", __func__);
278
279 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
280 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
281 /* Error state, transfer cannot occur */
282 debug("%s: ISR indicates error\n", __func__);
283 return FPGA_FAIL;
284 } else {
285 /* Clear out the status */
286 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
287 }
288 }
289
290 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
291 /* Clear the count of completed DMA transfers */
292 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
293 }
294
295 return FPGA_SUCCESS;
296 }
297
zynq_align_dma_buffer(u32 * buf,u32 len,u32 swap)298 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
299 {
300 u32 *new_buf;
301 u32 i;
302
303 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
304 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
305
306 /*
307 * This might be dangerous but permits to flash if
308 * ARCH_DMA_MINALIGN is greater than header size
309 */
310 if (new_buf > buf) {
311 debug("%s: Aligned buffer is after buffer start\n",
312 __func__);
313 new_buf -= ARCH_DMA_MINALIGN;
314 }
315 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
316 (u32)buf, (u32)new_buf, swap);
317
318 for (i = 0; i < (len/4); i++)
319 new_buf[i] = load_word(&buf[i], swap);
320
321 buf = new_buf;
322 } else if (swap != SWAP_DONE) {
323 /* For bitstream which are aligned */
324 u32 *new_buf = (u32 *)buf;
325
326 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
327 swap);
328
329 for (i = 0; i < (len/4); i++)
330 new_buf[i] = load_word(&buf[i], swap);
331 }
332
333 return buf;
334 }
335
zynq_validate_bitstream(xilinx_desc * desc,const void * buf,size_t bsize,u32 blocksize,u32 * swap,bitstream_type * bstype)336 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
337 size_t bsize, u32 blocksize, u32 *swap,
338 bitstream_type *bstype)
339 {
340 u32 *buf_start;
341 u32 diff;
342
343 buf_start = check_data((u8 *)buf, blocksize, swap);
344
345 if (!buf_start)
346 return FPGA_FAIL;
347
348 /* Check if data is postpone from start */
349 diff = (u32)buf_start - (u32)buf;
350 if (diff) {
351 printf("%s: Bitstream is not validated yet (diff %x)\n",
352 __func__, diff);
353 return FPGA_FAIL;
354 }
355
356 if ((u32)buf < SZ_1M) {
357 printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
358 __func__, (u32)buf);
359 return FPGA_FAIL;
360 }
361
362 if (zynq_dma_xfer_init(*bstype))
363 return FPGA_FAIL;
364
365 return 0;
366 }
367
zynq_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)368 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
369 bitstream_type bstype)
370 {
371 unsigned long ts; /* Timestamp */
372 u32 isr_status, swap;
373
374 /*
375 * send bsize inplace of blocksize as it was not a bitstream
376 * in chunks
377 */
378 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
379 &bstype))
380 return FPGA_FAIL;
381
382 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
383
384 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
385 debug("%s: Size = %zu\n", __func__, bsize);
386
387 /* flush(clean & invalidate) d-cache range buf */
388 flush_dcache_range((u32)buf, (u32)buf +
389 roundup(bsize, ARCH_DMA_MINALIGN));
390
391 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
392 return FPGA_FAIL;
393
394 isr_status = readl(&devcfg_base->int_sts);
395 /* Check FPGA configuration completion */
396 ts = get_timer(0);
397 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
398 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
399 printf("%s: Timeout wait for FPGA to config\n",
400 __func__);
401 return FPGA_FAIL;
402 }
403 isr_status = readl(&devcfg_base->int_sts);
404 }
405
406 debug("%s: FPGA config done\n", __func__);
407
408 if (bstype != BIT_PARTIAL)
409 zynq_slcr_devcfg_enable();
410
411 return FPGA_SUCCESS;
412 }
413
414 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
zynq_loadfs(xilinx_desc * desc,const void * buf,size_t bsize,fpga_fs_info * fsinfo)415 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
416 fpga_fs_info *fsinfo)
417 {
418 unsigned long ts; /* Timestamp */
419 u32 isr_status, swap;
420 u32 partialbit = 0;
421 loff_t blocksize, actread;
422 loff_t pos = 0;
423 int fstype;
424 char *interface, *dev_part, *filename;
425
426 blocksize = fsinfo->blocksize;
427 interface = fsinfo->interface;
428 dev_part = fsinfo->dev_part;
429 filename = fsinfo->filename;
430 fstype = fsinfo->fstype;
431
432 if (fs_set_blk_dev(interface, dev_part, fstype))
433 return FPGA_FAIL;
434
435 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
436 return FPGA_FAIL;
437
438 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
439 &partialbit))
440 return FPGA_FAIL;
441
442 dcache_disable();
443
444 do {
445 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
446
447 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
448 0xffffffff, 0))
449 return FPGA_FAIL;
450
451 bsize -= blocksize;
452 pos += blocksize;
453
454 if (fs_set_blk_dev(interface, dev_part, fstype))
455 return FPGA_FAIL;
456
457 if (bsize > blocksize) {
458 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
459 return FPGA_FAIL;
460 } else {
461 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
462 return FPGA_FAIL;
463 }
464 } while (bsize > blocksize);
465
466 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
467
468 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
469 return FPGA_FAIL;
470
471 dcache_enable();
472
473 isr_status = readl(&devcfg_base->int_sts);
474
475 /* Check FPGA configuration completion */
476 ts = get_timer(0);
477 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
478 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
479 printf("%s: Timeout wait for FPGA to config\n",
480 __func__);
481 return FPGA_FAIL;
482 }
483 isr_status = readl(&devcfg_base->int_sts);
484 }
485
486 debug("%s: FPGA config done\n", __func__);
487
488 if (!partialbit)
489 zynq_slcr_devcfg_enable();
490
491 return FPGA_SUCCESS;
492 }
493 #endif
494
495 struct xilinx_fpga_op zynq_op = {
496 .load = zynq_load,
497 #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
498 .loadfs = zynq_loadfs,
499 #endif
500 };
501
502 #ifdef CONFIG_CMD_ZYNQ_AES
503 /*
504 * Load the encrypted image from src addr and decrypt the image and
505 * place it back the decrypted image into dstaddr.
506 */
zynq_decrypt_load(u32 srcaddr,u32 srclen,u32 dstaddr,u32 dstlen)507 int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
508 {
509 if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
510 printf("%s: src and dst addr should be > 1M\n",
511 __func__);
512 return FPGA_FAIL;
513 }
514
515 if (zynq_dma_xfer_init(BIT_NONE)) {
516 printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
517 return FPGA_FAIL;
518 }
519
520 writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
521 &devcfg_base->ctrl);
522
523 debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
524 debug("%s: Size = %zu\n", __func__, srclen);
525
526 /* flush(clean & invalidate) d-cache range buf */
527 flush_dcache_range((u32)srcaddr, (u32)srcaddr +
528 roundup(srclen << 2, ARCH_DMA_MINALIGN));
529 /*
530 * Flush destination address range only if image is not
531 * bitstream.
532 */
533 flush_dcache_range((u32)dstaddr, (u32)dstaddr +
534 roundup(dstlen << 2, ARCH_DMA_MINALIGN));
535
536 if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
537 return FPGA_FAIL;
538
539 writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
540 &devcfg_base->ctrl);
541
542 return FPGA_SUCCESS;
543 }
544 #endif
545