1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012-2013, Xilinx, Michal Simek 4 * 5 * (C) Copyright 2002 6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 7 * Keith Outwater, keith_outwater@mvis.com 8 */ 9 10 /* 11 * Xilinx FPGA support 12 */ 13 14 #include <common.h> 15 #include <fpga.h> 16 #include <virtex2.h> 17 #include <spartan2.h> 18 #include <spartan3.h> 19 #include <zynqpl.h> 20 21 /* Local Static Functions */ 22 static int xilinx_validate(xilinx_desc *desc, char *fn); 23 24 /* ------------------------------------------------------------------------- */ 25 26 int fpga_is_partial_data(int devnum, size_t img_len) 27 { 28 const fpga_desc * const desc = fpga_get_desc(devnum); 29 xilinx_desc *desc_xilinx = desc->devdesc; 30 31 /* Check datasize against FPGA size */ 32 if (img_len >= desc_xilinx->size) 33 return 0; 34 35 /* datasize is smaller, must be partial data */ 36 return 1; 37 } 38 39 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 40 bitstream_type bstype) 41 { 42 unsigned int length; 43 unsigned int swapsize; 44 unsigned char *dataptr; 45 unsigned int i; 46 const fpga_desc *desc; 47 xilinx_desc *xdesc; 48 49 dataptr = (unsigned char *)fpgadata; 50 /* Find out fpga_description */ 51 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); 52 /* Assign xilinx device description */ 53 xdesc = desc->devdesc; 54 55 /* skip the first bytes of the bitsteam, their meaning is unknown */ 56 length = (*dataptr << 8) + *(dataptr + 1); 57 dataptr += 2; 58 dataptr += length; 59 60 /* get design name (identifier, length, string) */ 61 length = (*dataptr << 8) + *(dataptr + 1); 62 dataptr += 2; 63 if (*dataptr++ != 0x61) { 64 debug("%s: Design name id not recognized in bitstream\n", 65 __func__); 66 return FPGA_FAIL; 67 } 68 69 length = (*dataptr << 8) + *(dataptr + 1); 70 dataptr += 2; 71 printf(" design filename = \"%s\"\n", dataptr); 72 dataptr += length; 73 74 /* get part number (identifier, length, string) */ 75 if (*dataptr++ != 0x62) { 76 printf("%s: Part number id not recognized in bitstream\n", 77 __func__); 78 return FPGA_FAIL; 79 } 80 81 length = (*dataptr << 8) + *(dataptr + 1); 82 dataptr += 2; 83 84 if (xdesc->name) { 85 i = (ulong)strstr((char *)dataptr, xdesc->name); 86 if (!i) { 87 printf("%s: Wrong bitstream ID for this device\n", 88 __func__); 89 printf("%s: Bitstream ID %s, current device ID %d/%s\n", 90 __func__, dataptr, devnum, xdesc->name); 91 return FPGA_FAIL; 92 } 93 } else { 94 printf("%s: Please fill correct device ID to xilinx_desc\n", 95 __func__); 96 } 97 printf(" part number = \"%s\"\n", dataptr); 98 dataptr += length; 99 100 /* get date (identifier, length, string) */ 101 if (*dataptr++ != 0x63) { 102 printf("%s: Date identifier not recognized in bitstream\n", 103 __func__); 104 return FPGA_FAIL; 105 } 106 107 length = (*dataptr << 8) + *(dataptr+1); 108 dataptr += 2; 109 printf(" date = \"%s\"\n", dataptr); 110 dataptr += length; 111 112 /* get time (identifier, length, string) */ 113 if (*dataptr++ != 0x64) { 114 printf("%s: Time identifier not recognized in bitstream\n", 115 __func__); 116 return FPGA_FAIL; 117 } 118 119 length = (*dataptr << 8) + *(dataptr+1); 120 dataptr += 2; 121 printf(" time = \"%s\"\n", dataptr); 122 dataptr += length; 123 124 /* get fpga data length (identifier, length) */ 125 if (*dataptr++ != 0x65) { 126 printf("%s: Data length id not recognized in bitstream\n", 127 __func__); 128 return FPGA_FAIL; 129 } 130 swapsize = ((unsigned int) *dataptr << 24) + 131 ((unsigned int) *(dataptr + 1) << 16) + 132 ((unsigned int) *(dataptr + 2) << 8) + 133 ((unsigned int) *(dataptr + 3)); 134 dataptr += 4; 135 printf(" bytes in bitstream = %d\n", swapsize); 136 137 return fpga_load(devnum, dataptr, swapsize, bstype); 138 } 139 140 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, 141 bitstream_type bstype) 142 { 143 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 144 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 145 return FPGA_FAIL; 146 } 147 148 if (!desc->operations || !desc->operations->load) { 149 printf("%s: Missing load operation\n", __func__); 150 return FPGA_FAIL; 151 } 152 153 return desc->operations->load(desc, buf, bsize, bstype); 154 } 155 156 #if defined(CONFIG_CMD_FPGA_LOADFS) 157 int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, 158 fpga_fs_info *fpga_fsinfo) 159 { 160 if (!xilinx_validate(desc, (char *)__func__)) { 161 printf("%s: Invalid device descriptor\n", __func__); 162 return FPGA_FAIL; 163 } 164 165 if (!desc->operations || !desc->operations->loadfs) { 166 printf("%s: Missing loadfs operation\n", __func__); 167 return FPGA_FAIL; 168 } 169 170 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); 171 } 172 #endif 173 174 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) 175 { 176 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 177 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 178 return FPGA_FAIL; 179 } 180 181 if (!desc->operations || !desc->operations->dump) { 182 printf("%s: Missing dump operation\n", __func__); 183 return FPGA_FAIL; 184 } 185 186 return desc->operations->dump(desc, buf, bsize); 187 } 188 189 int xilinx_info(xilinx_desc *desc) 190 { 191 int ret_val = FPGA_FAIL; 192 193 if (xilinx_validate (desc, (char *)__FUNCTION__)) { 194 printf ("Family: \t"); 195 switch (desc->family) { 196 case xilinx_spartan2: 197 printf ("Spartan-II\n"); 198 break; 199 case xilinx_spartan3: 200 printf ("Spartan-III\n"); 201 break; 202 case xilinx_virtex2: 203 printf ("Virtex-II\n"); 204 break; 205 case xilinx_zynq: 206 printf("Zynq PL\n"); 207 break; 208 case xilinx_zynqmp: 209 printf("ZynqMP PL\n"); 210 break; 211 /* Add new family types here */ 212 default: 213 printf ("Unknown family type, %d\n", desc->family); 214 } 215 216 printf ("Interface type:\t"); 217 switch (desc->iface) { 218 case slave_serial: 219 printf ("Slave Serial\n"); 220 break; 221 case master_serial: /* Not used */ 222 printf ("Master Serial\n"); 223 break; 224 case slave_parallel: 225 printf ("Slave Parallel\n"); 226 break; 227 case jtag_mode: /* Not used */ 228 printf ("JTAG Mode\n"); 229 break; 230 case slave_selectmap: 231 printf ("Slave SelectMap Mode\n"); 232 break; 233 case master_selectmap: 234 printf ("Master SelectMap Mode\n"); 235 break; 236 case devcfg: 237 printf("Device configuration interface (Zynq)\n"); 238 break; 239 case csu_dma: 240 printf("csu_dma configuration interface (ZynqMP)\n"); 241 break; 242 /* Add new interface types here */ 243 default: 244 printf ("Unsupported interface type, %d\n", desc->iface); 245 } 246 247 printf("Device Size: \t%zd bytes\n" 248 "Cookie: \t0x%x (%d)\n", 249 desc->size, desc->cookie, desc->cookie); 250 if (desc->name) 251 printf("Device name: \t%s\n", desc->name); 252 253 if (desc->iface_fns) 254 printf ("Device Function Table @ 0x%p\n", desc->iface_fns); 255 else 256 printf ("No Device Function Table.\n"); 257 258 if (desc->operations && desc->operations->info) 259 desc->operations->info(desc); 260 261 ret_val = FPGA_SUCCESS; 262 } else { 263 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 264 } 265 266 return ret_val; 267 } 268 269 /* ------------------------------------------------------------------------- */ 270 271 static int xilinx_validate(xilinx_desc *desc, char *fn) 272 { 273 int ret_val = false; 274 275 if (desc) { 276 if ((desc->family > min_xilinx_type) && 277 (desc->family < max_xilinx_type)) { 278 if ((desc->iface > min_xilinx_iface_type) && 279 (desc->iface < max_xilinx_iface_type)) { 280 if (desc->size) { 281 ret_val = true; 282 } else 283 printf ("%s: NULL part size\n", fn); 284 } else 285 printf ("%s: Invalid Interface type, %d\n", 286 fn, desc->iface); 287 } else 288 printf ("%s: Invalid family type, %d\n", fn, desc->family); 289 } else 290 printf ("%s: NULL descriptor!\n", fn); 291 292 return ret_val; 293 } 294