xref: /openbmc/u-boot/drivers/fpga/xilinx.c (revision 7a78bd26)
1 /*
2  * (C) Copyright 2012-2013, Xilinx, Michal Simek
3  *
4  * (C) Copyright 2002
5  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
6  * Keith Outwater, keith_outwater@mvis.com
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 /*
12  *  Xilinx FPGA support
13  */
14 
15 #include <common.h>
16 #include <fpga.h>
17 #include <virtex2.h>
18 #include <spartan2.h>
19 #include <spartan3.h>
20 #include <zynqpl.h>
21 
22 /* Local Static Functions */
23 static int xilinx_validate(xilinx_desc *desc, char *fn);
24 
25 /* ------------------------------------------------------------------------- */
26 
27 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
28 		       bitstream_type bstype)
29 {
30 	unsigned int length;
31 	unsigned int swapsize;
32 	char buffer[80];
33 	unsigned char *dataptr;
34 	unsigned int i;
35 	const fpga_desc *desc;
36 	xilinx_desc *xdesc;
37 
38 	dataptr = (unsigned char *)fpgadata;
39 	/* Find out fpga_description */
40 	desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
41 	/* Assign xilinx device description */
42 	xdesc = desc->devdesc;
43 
44 	/* skip the first bytes of the bitsteam, their meaning is unknown */
45 	length = (*dataptr << 8) + *(dataptr + 1);
46 	dataptr += 2;
47 	dataptr += length;
48 
49 	/* get design name (identifier, length, string) */
50 	length = (*dataptr << 8) + *(dataptr + 1);
51 	dataptr += 2;
52 	if (*dataptr++ != 0x61) {
53 		debug("%s: Design name id not recognized in bitstream\n",
54 		      __func__);
55 		return FPGA_FAIL;
56 	}
57 
58 	length = (*dataptr << 8) + *(dataptr + 1);
59 	dataptr += 2;
60 	for (i = 0; i < length; i++)
61 		buffer[i] = *dataptr++;
62 
63 	printf("  design filename = \"%s\"\n", buffer);
64 
65 	/* get part number (identifier, length, string) */
66 	if (*dataptr++ != 0x62) {
67 		printf("%s: Part number id not recognized in bitstream\n",
68 		       __func__);
69 		return FPGA_FAIL;
70 	}
71 
72 	length = (*dataptr << 8) + *(dataptr + 1);
73 	dataptr += 2;
74 	for (i = 0; i < length; i++)
75 		buffer[i] = *dataptr++;
76 
77 	if (xdesc->name) {
78 		i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
79 		if (i) {
80 			printf("%s: Wrong bitstream ID for this device\n",
81 			       __func__);
82 			printf("%s: Bitstream ID %s, current device ID %d/%s\n",
83 			       __func__, buffer, devnum, xdesc->name);
84 			return FPGA_FAIL;
85 		}
86 	} else {
87 		printf("%s: Please fill correct device ID to xilinx_desc\n",
88 		       __func__);
89 	}
90 	printf("  part number = \"%s\"\n", buffer);
91 
92 	/* get date (identifier, length, string) */
93 	if (*dataptr++ != 0x63) {
94 		printf("%s: Date identifier not recognized in bitstream\n",
95 		       __func__);
96 		return FPGA_FAIL;
97 	}
98 
99 	length = (*dataptr << 8) + *(dataptr+1);
100 	dataptr += 2;
101 	for (i = 0; i < length; i++)
102 		buffer[i] = *dataptr++;
103 	printf("  date = \"%s\"\n", buffer);
104 
105 	/* get time (identifier, length, string) */
106 	if (*dataptr++ != 0x64) {
107 		printf("%s: Time identifier not recognized in bitstream\n",
108 		       __func__);
109 		return FPGA_FAIL;
110 	}
111 
112 	length = (*dataptr << 8) + *(dataptr+1);
113 	dataptr += 2;
114 	for (i = 0; i < length; i++)
115 		buffer[i] = *dataptr++;
116 	printf("  time = \"%s\"\n", buffer);
117 
118 	/* get fpga data length (identifier, length) */
119 	if (*dataptr++ != 0x65) {
120 		printf("%s: Data length id not recognized in bitstream\n",
121 		       __func__);
122 		return FPGA_FAIL;
123 	}
124 	swapsize = ((unsigned int) *dataptr << 24) +
125 		   ((unsigned int) *(dataptr + 1) << 16) +
126 		   ((unsigned int) *(dataptr + 2) << 8) +
127 		   ((unsigned int) *(dataptr + 3));
128 	dataptr += 4;
129 	printf("  bytes in bitstream = %d\n", swapsize);
130 
131 	return fpga_load(devnum, dataptr, swapsize, bstype);
132 }
133 
134 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
135 		bitstream_type bstype)
136 {
137 	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
138 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
139 		return FPGA_FAIL;
140 	}
141 
142 	return desc->operations->load(desc, buf, bsize, bstype);
143 }
144 
145 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
146 {
147 	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
148 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
149 		return FPGA_FAIL;
150 	}
151 
152 	return desc->operations->dump(desc, buf, bsize);
153 }
154 
155 int xilinx_info(xilinx_desc *desc)
156 {
157 	int ret_val = FPGA_FAIL;
158 
159 	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
160 		printf ("Family:        \t");
161 		switch (desc->family) {
162 		case xilinx_spartan2:
163 			printf ("Spartan-II\n");
164 			break;
165 		case xilinx_spartan3:
166 			printf ("Spartan-III\n");
167 			break;
168 		case xilinx_virtex2:
169 			printf ("Virtex-II\n");
170 			break;
171 		case xilinx_zynq:
172 			printf("Zynq PL\n");
173 			break;
174 			/* Add new family types here */
175 		default:
176 			printf ("Unknown family type, %d\n", desc->family);
177 		}
178 
179 		printf ("Interface type:\t");
180 		switch (desc->iface) {
181 		case slave_serial:
182 			printf ("Slave Serial\n");
183 			break;
184 		case master_serial:	/* Not used */
185 			printf ("Master Serial\n");
186 			break;
187 		case slave_parallel:
188 			printf ("Slave Parallel\n");
189 			break;
190 		case jtag_mode:		/* Not used */
191 			printf ("JTAG Mode\n");
192 			break;
193 		case slave_selectmap:
194 			printf ("Slave SelectMap Mode\n");
195 			break;
196 		case master_selectmap:
197 			printf ("Master SelectMap Mode\n");
198 			break;
199 		case devcfg:
200 			printf("Device configuration interface (Zynq)\n");
201 			break;
202 			/* Add new interface types here */
203 		default:
204 			printf ("Unsupported interface type, %d\n", desc->iface);
205 		}
206 
207 		printf ("Device Size:   \t%d bytes\n"
208 				"Cookie:        \t0x%x (%d)\n",
209 				desc->size, desc->cookie, desc->cookie);
210 		if (desc->name)
211 			printf("Device name:   \t%s\n", desc->name);
212 
213 		if (desc->iface_fns) {
214 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
215 			desc->operations->info(desc);
216 		} else
217 			printf ("No Device Function Table.\n");
218 
219 		ret_val = FPGA_SUCCESS;
220 	} else {
221 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
222 	}
223 
224 	return ret_val;
225 }
226 
227 /* ------------------------------------------------------------------------- */
228 
229 static int xilinx_validate(xilinx_desc *desc, char *fn)
230 {
231 	int ret_val = false;
232 
233 	if (desc) {
234 		if ((desc->family > min_xilinx_type) &&
235 			(desc->family < max_xilinx_type)) {
236 			if ((desc->iface > min_xilinx_iface_type) &&
237 				(desc->iface < max_xilinx_iface_type)) {
238 				if (desc->size) {
239 					ret_val = true;
240 				} else
241 					printf ("%s: NULL part size\n", fn);
242 			} else
243 				printf ("%s: Invalid Interface type, %d\n",
244 						fn, desc->iface);
245 		} else
246 			printf ("%s: Invalid family type, %d\n", fn, desc->family);
247 	} else
248 		printf ("%s: NULL descriptor!\n", fn);
249 
250 	return ret_val;
251 }
252