1 /* 2 * (C) Copyright 2012-2013, Xilinx, Michal Simek 3 * 4 * (C) Copyright 2002 5 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 6 * Keith Outwater, keith_outwater@mvis.com 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 /* 12 * Xilinx FPGA support 13 */ 14 15 #include <common.h> 16 #include <fpga.h> 17 #include <virtex2.h> 18 #include <spartan2.h> 19 #include <spartan3.h> 20 #include <zynqpl.h> 21 22 /* Local Static Functions */ 23 static int xilinx_validate(xilinx_desc *desc, char *fn); 24 25 /* ------------------------------------------------------------------------- */ 26 27 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 28 bitstream_type bstype) 29 { 30 unsigned int length; 31 unsigned int swapsize; 32 unsigned char *dataptr; 33 unsigned int i; 34 const fpga_desc *desc; 35 xilinx_desc *xdesc; 36 37 dataptr = (unsigned char *)fpgadata; 38 /* Find out fpga_description */ 39 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); 40 /* Assign xilinx device description */ 41 xdesc = desc->devdesc; 42 43 /* skip the first bytes of the bitsteam, their meaning is unknown */ 44 length = (*dataptr << 8) + *(dataptr + 1); 45 dataptr += 2; 46 dataptr += length; 47 48 /* get design name (identifier, length, string) */ 49 length = (*dataptr << 8) + *(dataptr + 1); 50 dataptr += 2; 51 if (*dataptr++ != 0x61) { 52 debug("%s: Design name id not recognized in bitstream\n", 53 __func__); 54 return FPGA_FAIL; 55 } 56 57 length = (*dataptr << 8) + *(dataptr + 1); 58 dataptr += 2; 59 printf(" design filename = \"%s\"\n", dataptr); 60 dataptr += length; 61 62 /* get part number (identifier, length, string) */ 63 if (*dataptr++ != 0x62) { 64 printf("%s: Part number id not recognized in bitstream\n", 65 __func__); 66 return FPGA_FAIL; 67 } 68 69 length = (*dataptr << 8) + *(dataptr + 1); 70 dataptr += 2; 71 72 if (xdesc->name) { 73 i = (ulong)strstr((char *)dataptr, xdesc->name); 74 if (!i) { 75 printf("%s: Wrong bitstream ID for this device\n", 76 __func__); 77 printf("%s: Bitstream ID %s, current device ID %d/%s\n", 78 __func__, dataptr, devnum, xdesc->name); 79 return FPGA_FAIL; 80 } 81 } else { 82 printf("%s: Please fill correct device ID to xilinx_desc\n", 83 __func__); 84 } 85 printf(" part number = \"%s\"\n", dataptr); 86 dataptr += length; 87 88 /* get date (identifier, length, string) */ 89 if (*dataptr++ != 0x63) { 90 printf("%s: Date identifier not recognized in bitstream\n", 91 __func__); 92 return FPGA_FAIL; 93 } 94 95 length = (*dataptr << 8) + *(dataptr+1); 96 dataptr += 2; 97 printf(" date = \"%s\"\n", dataptr); 98 dataptr += length; 99 100 /* get time (identifier, length, string) */ 101 if (*dataptr++ != 0x64) { 102 printf("%s: Time identifier not recognized in bitstream\n", 103 __func__); 104 return FPGA_FAIL; 105 } 106 107 length = (*dataptr << 8) + *(dataptr+1); 108 dataptr += 2; 109 printf(" time = \"%s\"\n", dataptr); 110 dataptr += length; 111 112 /* get fpga data length (identifier, length) */ 113 if (*dataptr++ != 0x65) { 114 printf("%s: Data length id not recognized in bitstream\n", 115 __func__); 116 return FPGA_FAIL; 117 } 118 swapsize = ((unsigned int) *dataptr << 24) + 119 ((unsigned int) *(dataptr + 1) << 16) + 120 ((unsigned int) *(dataptr + 2) << 8) + 121 ((unsigned int) *(dataptr + 3)); 122 dataptr += 4; 123 printf(" bytes in bitstream = %d\n", swapsize); 124 125 return fpga_load(devnum, dataptr, swapsize, bstype); 126 } 127 128 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, 129 bitstream_type bstype) 130 { 131 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 132 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 133 return FPGA_FAIL; 134 } 135 136 if (!desc->operations || !desc->operations->load) { 137 printf("%s: Missing load operation\n", __func__); 138 return FPGA_FAIL; 139 } 140 141 return desc->operations->load(desc, buf, bsize, bstype); 142 } 143 144 #if defined(CONFIG_CMD_FPGA_LOADFS) 145 int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, 146 fpga_fs_info *fpga_fsinfo) 147 { 148 if (!xilinx_validate(desc, (char *)__func__)) { 149 printf("%s: Invalid device descriptor\n", __func__); 150 return FPGA_FAIL; 151 } 152 153 if (!desc->operations || !desc->operations->loadfs) { 154 printf("%s: Missing loadfs operation\n", __func__); 155 return FPGA_FAIL; 156 } 157 158 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); 159 } 160 #endif 161 162 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) 163 { 164 if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 165 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 166 return FPGA_FAIL; 167 } 168 169 if (!desc->operations || !desc->operations->dump) { 170 printf("%s: Missing dump operation\n", __func__); 171 return FPGA_FAIL; 172 } 173 174 return desc->operations->dump(desc, buf, bsize); 175 } 176 177 int xilinx_info(xilinx_desc *desc) 178 { 179 int ret_val = FPGA_FAIL; 180 181 if (xilinx_validate (desc, (char *)__FUNCTION__)) { 182 printf ("Family: \t"); 183 switch (desc->family) { 184 case xilinx_spartan2: 185 printf ("Spartan-II\n"); 186 break; 187 case xilinx_spartan3: 188 printf ("Spartan-III\n"); 189 break; 190 case xilinx_virtex2: 191 printf ("Virtex-II\n"); 192 break; 193 case xilinx_zynq: 194 printf("Zynq PL\n"); 195 break; 196 case xilinx_zynqmp: 197 printf("ZynqMP PL\n"); 198 break; 199 /* Add new family types here */ 200 default: 201 printf ("Unknown family type, %d\n", desc->family); 202 } 203 204 printf ("Interface type:\t"); 205 switch (desc->iface) { 206 case slave_serial: 207 printf ("Slave Serial\n"); 208 break; 209 case master_serial: /* Not used */ 210 printf ("Master Serial\n"); 211 break; 212 case slave_parallel: 213 printf ("Slave Parallel\n"); 214 break; 215 case jtag_mode: /* Not used */ 216 printf ("JTAG Mode\n"); 217 break; 218 case slave_selectmap: 219 printf ("Slave SelectMap Mode\n"); 220 break; 221 case master_selectmap: 222 printf ("Master SelectMap Mode\n"); 223 break; 224 case devcfg: 225 printf("Device configuration interface (Zynq)\n"); 226 break; 227 case csu_dma: 228 printf("csu_dma configuration interface (ZynqMP)\n"); 229 break; 230 /* Add new interface types here */ 231 default: 232 printf ("Unsupported interface type, %d\n", desc->iface); 233 } 234 235 printf("Device Size: \t%zd bytes\n" 236 "Cookie: \t0x%x (%d)\n", 237 desc->size, desc->cookie, desc->cookie); 238 if (desc->name) 239 printf("Device name: \t%s\n", desc->name); 240 241 if (desc->iface_fns) 242 printf ("Device Function Table @ 0x%p\n", desc->iface_fns); 243 else 244 printf ("No Device Function Table.\n"); 245 246 if (desc->operations && desc->operations->info) 247 desc->operations->info(desc); 248 249 ret_val = FPGA_SUCCESS; 250 } else { 251 printf ("%s: Invalid device descriptor\n", __FUNCTION__); 252 } 253 254 return ret_val; 255 } 256 257 /* ------------------------------------------------------------------------- */ 258 259 static int xilinx_validate(xilinx_desc *desc, char *fn) 260 { 261 int ret_val = false; 262 263 if (desc) { 264 if ((desc->family > min_xilinx_type) && 265 (desc->family < max_xilinx_type)) { 266 if ((desc->iface > min_xilinx_iface_type) && 267 (desc->iface < max_xilinx_iface_type)) { 268 if (desc->size) { 269 ret_val = true; 270 } else 271 printf ("%s: NULL part size\n", fn); 272 } else 273 printf ("%s: Invalid Interface type, %d\n", 274 fn, desc->iface); 275 } else 276 printf ("%s: Invalid family type, %d\n", fn, desc->family); 277 } else 278 printf ("%s: NULL descriptor!\n", fn); 279 280 return ret_val; 281 } 282