1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007 4 * Eran Liberty, Extricom , eran.liberty@gmail.com 5 */ 6 7 #include <common.h> /* core U-Boot definitions */ 8 #include <altera.h> 9 10 int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, 11 int isSerial, int isSecure); 12 int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize); 13 14 /****************************************************************/ 15 /* Stratix II Generic Implementation */ 16 int StratixII_load (Altera_desc * desc, void *buf, size_t bsize) 17 { 18 int ret_val = FPGA_FAIL; 19 20 switch (desc->iface) { 21 case passive_serial: 22 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0); 23 break; 24 case fast_passive_parallel: 25 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0); 26 break; 27 case fast_passive_parallel_security: 28 ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1); 29 break; 30 31 /* Add new interface types here */ 32 default: 33 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, 34 desc->iface); 35 } 36 return ret_val; 37 } 38 39 int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize) 40 { 41 int ret_val = FPGA_FAIL; 42 43 switch (desc->iface) { 44 case passive_serial: 45 case fast_passive_parallel: 46 case fast_passive_parallel_security: 47 ret_val = StratixII_ps_fpp_dump (desc, buf, bsize); 48 break; 49 /* Add new interface types here */ 50 default: 51 printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, 52 desc->iface); 53 } 54 return ret_val; 55 } 56 57 int StratixII_info (Altera_desc * desc) 58 { 59 return FPGA_SUCCESS; 60 } 61 62 int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) 63 { 64 printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); 65 return FPGA_FAIL; 66 } 67 68 int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, 69 int isSerial, int isSecure) 70 { 71 altera_board_specific_func *fns; 72 int cookie; 73 int ret_val = FPGA_FAIL; 74 int bytecount; 75 char *buff = buf; 76 int i; 77 78 if (!desc) { 79 printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__); 80 return FPGA_FAIL; 81 } 82 if (!buff) { 83 printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__); 84 return FPGA_FAIL; 85 } 86 if (!bsize) { 87 printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__); 88 return FPGA_FAIL; 89 } 90 if (!desc->iface_fns) { 91 printf 92 ("%s(%d) Altera_desc function interface table is missing\n", 93 __FUNCTION__, __LINE__); 94 return FPGA_FAIL; 95 } 96 fns = (altera_board_specific_func *) (desc->iface_fns); 97 cookie = desc->cookie; 98 99 if (! 100 (fns->config && fns->status && fns->done && fns->data 101 && fns->abort)) { 102 printf 103 ("%s(%d) Missing some function in the function interface table\n", 104 __FUNCTION__, __LINE__); 105 return FPGA_FAIL; 106 } 107 108 /* 1. give board specific a chance to do anything before we start */ 109 if (fns->pre) { 110 if ((ret_val = fns->pre (cookie)) < 0) { 111 return ret_val; 112 } 113 } 114 115 /* from this point on we must fail gracfully by calling lower layer abort */ 116 117 /* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */ 118 fns->config (0, 1, cookie); 119 udelay (5); /* nCONFIG low pulse width 2usec */ 120 fns->config (1, 1, cookie); 121 udelay (100); /* nCONFIG high to first rising edge on DCLK */ 122 123 /* 3. Start the Data cycle with clk deasserted */ 124 bytecount = 0; 125 fns->clk (0, 1, cookie); 126 127 printf ("loading to fpga "); 128 while (bytecount < bsize) { 129 /* 3.1 check stratix has not signaled us an error */ 130 if (fns->status (cookie) != 1) { 131 printf 132 ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n", 133 __FUNCTION__, __LINE__, bytecount); 134 fns->abort (cookie); 135 return FPGA_FAIL; 136 } 137 if (isSerial) { 138 int i; 139 uint8_t data = buff[bytecount++]; 140 for (i = 0; i < 8; i++) { 141 /* 3.2(ps) put data on the bus */ 142 fns->data ((data >> i) & 1, 1, cookie); 143 144 /* 3.3(ps) clock once */ 145 fns->clk (1, 1, cookie); 146 fns->clk (0, 1, cookie); 147 } 148 } else { 149 /* 3.2(fpp) put data on the bus */ 150 fns->data (buff[bytecount++], 1, cookie); 151 152 /* 3.3(fpp) clock once */ 153 fns->clk (1, 1, cookie); 154 fns->clk (0, 1, cookie); 155 156 /* 3.4(fpp) for secure cycle push 3 more clocks */ 157 for (i = 0; isSecure && i < 3; i++) { 158 fns->clk (1, 1, cookie); 159 fns->clk (0, 1, cookie); 160 } 161 } 162 163 /* 3.5 while clk is deasserted it is safe to print some progress indication */ 164 if ((bytecount % (bsize / 100)) == 0) { 165 printf ("\b\b\b%02d\%", bytecount * 100 / bsize); 166 } 167 } 168 169 /* 4. Set one last clock and check conf done signal */ 170 fns->clk (1, 1, cookie); 171 udelay (100); 172 if (!fns->done (cookie)) { 173 printf (" error!.\n"); 174 fns->abort (cookie); 175 return FPGA_FAIL; 176 } else { 177 printf ("\b\b\b done.\n"); 178 } 179 180 /* 5. call lower layer post configuration */ 181 if (fns->post) { 182 if ((ret_val = fns->post (cookie)) < 0) { 183 fns->abort (cookie); 184 return ret_val; 185 } 186 } 187 188 return FPGA_SUCCESS; 189 } 190