1 /* 2 * (C) Copyright 2006 3 * Heiko Schocher, hs@denx.de 4 * Based on ACE1XK.c 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 * 24 */ 25 26 #include <common.h> /* core U-Boot definitions */ 27 #include <altera.h> 28 #include <ACEX1K.h> /* ACEX device family */ 29 30 /* Define FPGA_DEBUG to get debug printf's */ 31 #ifdef FPGA_DEBUG 32 #define PRINTF(fmt,args...) printf (fmt ,##args) 33 #else 34 #define PRINTF(fmt,args...) 35 #endif 36 37 /* Note: The assumption is that we cannot possibly run fast enough to 38 * overrun the device (the Slave Parallel mode can free run at 50MHz). 39 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in 40 * the board config file to slow things down. 41 */ 42 #ifndef CONFIG_FPGA_DELAY 43 #define CONFIG_FPGA_DELAY() 44 #endif 45 46 #ifndef CONFIG_SYS_FPGA_WAIT 47 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ 48 #endif 49 50 static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); 51 static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); 52 /* static int CYC2_ps_info( Altera_desc *desc ); */ 53 54 /* ------------------------------------------------------------------------- */ 55 /* CYCLON2 Generic Implementation */ 56 int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) 57 { 58 int ret_val = FPGA_FAIL; 59 60 switch (desc->iface) { 61 case passive_serial: 62 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); 63 ret_val = CYC2_ps_load (desc, buf, bsize); 64 break; 65 66 case fast_passive_parallel: 67 /* Fast Passive Parallel (FPP) and PS only differ in what is 68 * done in the write() callback. Use the existing PS load 69 * function for FPP, too. 70 */ 71 PRINTF ("%s: Launching Fast Passive Parallel Loader\n", 72 __FUNCTION__); 73 ret_val = CYC2_ps_load(desc, buf, bsize); 74 break; 75 76 /* Add new interface types here */ 77 78 default: 79 printf ("%s: Unsupported interface type, %d\n", 80 __FUNCTION__, desc->iface); 81 } 82 83 return ret_val; 84 } 85 86 int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) 87 { 88 int ret_val = FPGA_FAIL; 89 90 switch (desc->iface) { 91 case passive_serial: 92 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); 93 ret_val = CYC2_ps_dump (desc, buf, bsize); 94 break; 95 96 /* Add new interface types here */ 97 98 default: 99 printf ("%s: Unsupported interface type, %d\n", 100 __FUNCTION__, desc->iface); 101 } 102 103 return ret_val; 104 } 105 106 int CYC2_info( Altera_desc *desc ) 107 { 108 return FPGA_SUCCESS; 109 } 110 111 /* ------------------------------------------------------------------------- */ 112 /* CYCLON2 Passive Serial Generic Implementation */ 113 static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) 114 { 115 int ret_val = FPGA_FAIL; /* assume the worst */ 116 Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; 117 int ret = 0; 118 119 PRINTF ("%s: start with interface functions @ 0x%p\n", 120 __FUNCTION__, fn); 121 122 if (fn) { 123 int cookie = desc->cookie; /* make a local copy */ 124 unsigned long ts; /* timestamp */ 125 126 PRINTF ("%s: Function Table:\n" 127 "ptr:\t0x%p\n" 128 "struct: 0x%p\n" 129 "config:\t0x%p\n" 130 "status:\t0x%p\n" 131 "write:\t0x%p\n" 132 "done:\t0x%p\n\n", 133 __FUNCTION__, &fn, fn, fn->config, fn->status, 134 fn->write, fn->done); 135 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK 136 printf ("Loading FPGA Device %d...", cookie); 137 #endif 138 139 /* 140 * Run the pre configuration function if there is one. 141 */ 142 if (*fn->pre) { 143 (*fn->pre) (cookie); 144 } 145 146 /* Establish the initial state */ 147 (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ 148 149 udelay(2); /* T_cfg > 2us */ 150 151 /* Wait for nSTATUS to be asserted */ 152 ts = get_timer (0); /* get current time */ 153 do { 154 CONFIG_FPGA_DELAY (); 155 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ 156 puts ("** Timeout waiting for STATUS to go high.\n"); 157 (*fn->abort) (cookie); 158 return FPGA_FAIL; 159 } 160 } while (!(*fn->status) (cookie)); 161 162 /* Get ready for the burn */ 163 CONFIG_FPGA_DELAY (); 164 165 ret = (*fn->write) (buf, bsize, TRUE, cookie); 166 if (ret) { 167 puts ("** Write failed.\n"); 168 (*fn->abort) (cookie); 169 return FPGA_FAIL; 170 } 171 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK 172 puts(" OK? ..."); 173 #endif 174 175 CONFIG_FPGA_DELAY (); 176 177 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK 178 putc (' '); /* terminate the dotted line */ 179 #endif 180 181 /* 182 * Checking FPGA's CONF_DONE signal - correctly booted ? 183 */ 184 185 if ( ! (*fn->done) (cookie) ) { 186 puts ("** Booting failed! CONF_DONE is still deasserted.\n"); 187 (*fn->abort) (cookie); 188 return (FPGA_FAIL); 189 } 190 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK 191 puts(" OK\n"); 192 #endif 193 194 ret_val = FPGA_SUCCESS; 195 196 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK 197 if (ret_val == FPGA_SUCCESS) { 198 puts ("Done.\n"); 199 } 200 else { 201 puts ("Fail.\n"); 202 } 203 #endif 204 (*fn->post) (cookie); 205 206 } else { 207 printf ("%s: NULL Interface function table!\n", __FUNCTION__); 208 } 209 210 return ret_val; 211 } 212 213 static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) 214 { 215 /* Readback is only available through the Slave Parallel and */ 216 /* boundary-scan interfaces. */ 217 printf ("%s: Passive Serial Dumping is unavailable\n", 218 __FUNCTION__); 219 return FPGA_FAIL; 220 } 221