1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD# 2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD# (C) Copyright 2008 3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD# Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD# 51a459660SWolfgang Denk# SPDX-License-Identifier: GPL-2.0+ 6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD# 7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 8c8aa7dfcSJean-Christophe PLAGNIOL-VILLARDifdef CONFIG_FPGA 9*710f1d3dSMasahiro Yamadaobj-y += fpga.o 10*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o 11*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o 12*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o 13*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o 14*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_XILINX) += xilinx.o 15*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o 16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARDifdef CONFIG_FPGA_ALTERA 17*710f1d3dSMasahiro Yamadaobj-y += altera.o 18*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o 19*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o 20*710f1d3dSMasahiro Yamadaobj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o 21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARDendif 22c8aa7dfcSJean-Christophe PLAGNIOL-VILLARDendif 23