1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2008 by NXP Semiconductors 4 * @Author: Kevin Wells 5 * @Descr: LPC3250 DMA controller interface support functions 6 * 7 * Copyright (c) 2015 Tyco Fire Protection Products. 8 */ 9 10 #include <common.h> 11 #include <errno.h> 12 #include <asm/arch/dma.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/clk.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/io.h> 17 18 /* DMA controller channel register structure */ 19 struct dmac_chan_reg { 20 u32 src_addr; 21 u32 dest_addr; 22 u32 lli; 23 u32 control; 24 u32 config_ch; 25 u32 reserved[3]; 26 }; 27 28 /* DMA controller register structures */ 29 struct dma_reg { 30 u32 int_stat; 31 u32 int_tc_stat; 32 u32 int_tc_clear; 33 u32 int_err_stat; 34 u32 int_err_clear; 35 u32 raw_tc_stat; 36 u32 raw_err_stat; 37 u32 chan_enable; 38 u32 sw_burst_req; 39 u32 sw_single_req; 40 u32 sw_last_burst_req; 41 u32 sw_last_single_req; 42 u32 config; 43 u32 sync; 44 u32 reserved[50]; 45 struct dmac_chan_reg dma_chan[8]; 46 }; 47 48 #define DMA_NO_OF_CHANNELS 8 49 50 /* config register definitions */ 51 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */ 52 53 static u32 alloc_ch; 54 55 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; 56 57 int lpc32xx_dma_get_channel(void) 58 { 59 int i; 60 61 if (!alloc_ch) { /* First time caller */ 62 /* 63 * DMA clock are enable by "lpc32xx_dma_init()" and should 64 * be call by board "board_early_init_f()" function. 65 */ 66 67 /* 68 * Make sure DMA controller and all channels are disabled. 69 * Controller is in little-endian mode. Disable sync signals. 70 */ 71 writel(0, &dma->config); 72 writel(0, &dma->sync); 73 74 /* Clear interrupt and error statuses */ 75 writel(0xFF, &dma->int_tc_clear); 76 writel(0xFF, &dma->raw_tc_stat); 77 writel(0xFF, &dma->int_err_clear); 78 writel(0xFF, &dma->raw_err_stat); 79 80 /* Enable DMA controller */ 81 writel(DMAC_CTRL_ENABLE, &dma->config); 82 } 83 84 i = ffz(alloc_ch); 85 86 /* Check if all the available channels are busy */ 87 if (unlikely(i == DMA_NO_OF_CHANNELS)) 88 return -1; 89 alloc_ch |= BIT_MASK(i); 90 return i; 91 } 92 93 int lpc32xx_dma_start_xfer(unsigned int channel, 94 const struct lpc32xx_dmac_ll *desc, u32 config) 95 { 96 if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) || 97 (channel >= DMA_NO_OF_CHANNELS))) { 98 pr_err("Request for xfer on unallocated channel %d", channel); 99 return -1; 100 } 101 writel(BIT_MASK(channel), &dma->int_tc_clear); 102 writel(BIT_MASK(channel), &dma->int_err_clear); 103 writel(desc->dma_src, &dma->dma_chan[channel].src_addr); 104 writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); 105 writel(desc->next_lli, &dma->dma_chan[channel].lli); 106 writel(desc->next_ctrl, &dma->dma_chan[channel].control); 107 writel(config, &dma->dma_chan[channel].config_ch); 108 109 return 0; 110 } 111 112 int lpc32xx_dma_wait_status(unsigned int channel) 113 { 114 unsigned long start; 115 u32 reg; 116 117 /* Check if given channel is valid */ 118 if (unlikely(channel >= DMA_NO_OF_CHANNELS)) { 119 pr_err("Request for status on unallocated channel %d", channel); 120 return -1; 121 } 122 123 start = get_timer(0); 124 while (1) { 125 reg = readl(&dma->raw_tc_stat); 126 reg |= readl(dma->raw_err_stat); 127 if (reg & BIT_MASK(channel)) 128 break; 129 130 if (get_timer(start) > CONFIG_SYS_HZ) { 131 pr_err("DMA status timeout channel %d\n", channel); 132 return -ETIMEDOUT; 133 } 134 udelay(1); 135 } 136 137 if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) { 138 setbits_le32(&dma->int_err_clear, BIT_MASK(channel)); 139 setbits_le32(&dma->raw_err_stat, BIT_MASK(channel)); 140 pr_err("DMA error on channel %d\n", channel); 141 return -1; 142 } 143 setbits_le32(&dma->int_tc_clear, BIT_MASK(channel)); 144 setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel)); 145 return 0; 146 } 147