xref: /openbmc/u-boot/drivers/dma/fsl_dma.c (revision dd63fbc7)
1 /*
2  * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3  * (C) Copyright 2002, 2003 Motorola Inc.
4  * Xianghua Xiao (X.Xiao@motorola.com)
5  *
6  * (C) Copyright 2000
7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <config.h>
13 #include <common.h>
14 #include <asm/io.h>
15 #include <asm/fsl_dma.h>
16 
17 /* Controller can only transfer 2^26 - 1 bytes at a time */
18 #define FSL_DMA_MAX_SIZE	(0x3ffffff)
19 
20 #if defined(CONFIG_MPC83xx)
21 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
22 #else
23 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
24 #endif
25 
26 
27 #if defined(CONFIG_MPC83xx)
28 dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
29 #elif defined(CONFIG_MPC85xx)
30 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
31 #elif defined(CONFIG_MPC86xx)
32 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
33 #else
34 #error "Freescale DMA engine not supported on your processor"
35 #endif
36 
37 static void dma_sync(void)
38 {
39 #if defined(CONFIG_MPC85xx)
40 	asm("sync; isync; msync");
41 #elif defined(CONFIG_MPC86xx)
42 	asm("sync; isync");
43 #endif
44 }
45 
46 static void out_dma32(volatile unsigned *addr, int val)
47 {
48 #if defined(CONFIG_MPC83xx)
49 	out_le32(addr, val);
50 #else
51 	out_be32(addr, val);
52 #endif
53 }
54 
55 static uint in_dma32(volatile unsigned *addr)
56 {
57 #if defined(CONFIG_MPC83xx)
58 	return in_le32(addr);
59 #else
60 	return in_be32(addr);
61 #endif
62 }
63 
64 static uint dma_check(void) {
65 	volatile fsl_dma_t *dma = &dma_base->dma[0];
66 	uint status;
67 
68 	/* While the channel is busy, spin */
69 	do {
70 		status = in_dma32(&dma->sr);
71 	} while (status & FSL_DMA_SR_CB);
72 
73 	/* clear MR[CS] channel start bit */
74 	out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
75 	dma_sync();
76 
77 	if (status != 0)
78 		printf ("DMA Error: status = %x\n", status);
79 
80 	return status;
81 }
82 
83 #if !defined(CONFIG_MPC83xx)
84 void dma_init(void) {
85 	volatile fsl_dma_t *dma = &dma_base->dma[0];
86 
87 	out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
88 	out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
89 	out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
90 	dma_sync();
91 }
92 #endif
93 
94 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
95 	volatile fsl_dma_t *dma = &dma_base->dma[0];
96 	uint xfer_size;
97 
98 	while (count) {
99 		xfer_size = min(FSL_DMA_MAX_SIZE, count);
100 
101 		out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
102 		out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
103 #if !defined(CONFIG_MPC83xx)
104 		out_dma32(&dma->satr,
105 			in_dma32(&dma->satr) | (u32)((u64)src >> 32));
106 		out_dma32(&dma->datr,
107 			in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
108 #endif
109 		out_dma32(&dma->bcr, xfer_size);
110 		dma_sync();
111 
112 		/* Prepare mode register */
113 		out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
114 		dma_sync();
115 
116 		/* Start the transfer */
117 		out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
118 
119 		count -= xfer_size;
120 		src += xfer_size;
121 		dest += xfer_size;
122 
123 		dma_sync();
124 
125 		if (dma_check())
126 			return -1;
127 	}
128 
129 	return 0;
130 }
131 
132 /*
133  * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134  * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
135  */
136 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&	\
137 	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||		\
138 	(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
139 void dma_meminit(uint val, uint size)
140 {
141 	uint *p = 0;
142 	uint i = 0;
143 
144 	for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 		if (((uint)p & 0x1f) == 0)
146 			ppcDcbz((ulong)p);
147 
148 		*p = (uint)CONFIG_MEM_INIT_VALUE;
149 
150 		if (((uint)p & 0x1c) == 0x1c)
151 			ppcDcbf((ulong)p);
152 	}
153 
154 	dmacpy(0x002000, 0, 0x002000); /* 8K */
155 	dmacpy(0x004000, 0, 0x004000); /* 16K */
156 	dmacpy(0x008000, 0, 0x008000); /* 32K */
157 	dmacpy(0x010000, 0, 0x010000); /* 64K */
158 	dmacpy(0x020000, 0, 0x020000); /* 128K */
159 	dmacpy(0x040000, 0, 0x040000); /* 256K */
160 	dmacpy(0x080000, 0, 0x080000); /* 512K */
161 	dmacpy(0x100000, 0, 0x100000); /* 1M */
162 	dmacpy(0x200000, 0, 0x200000); /* 2M */
163 	dmacpy(0x400000, 0, 0x400000); /* 4M */
164 
165 	for (i = 1; i < size / 0x800000; i++)
166 		dmacpy((0x800000 * i), 0, 0x800000);
167 }
168 #endif
169