1 /* 2 * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 */ 7 8 #ifndef __MICROCHIP_DDR2_TIMING_H 9 #define __MICROCHIP_DDR2_TIMING_H 10 11 /* MPLL freq is 400MHz */ 12 #define T_CK 2500 /* 2500 psec */ 13 #define T_CK_CTRL (T_CK * 2) 14 15 /* Burst length in cycles */ 16 #define BL 2 17 /* default CAS latency for all speed grades */ 18 #define RL 5 19 /* default write latency for all speed grades = CL-1 */ 20 #define WL 4 21 22 /* From Micron MT47H64M16HR-3 data sheet */ 23 #define T_RFC_MIN 127500 /* psec */ 24 #define T_WR 15000 /* psec */ 25 #define T_RP 12500 /* psec */ 26 #define T_RCD 12500 /* psec */ 27 #define T_RRD 7500 /* psec */ 28 /* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */ 29 #define T_RRD_TCK 2 30 #define T_WTR 7500 /* psec */ 31 /* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */ 32 #define T_WTR_TCK 2 33 #define T_RTP 7500 /* psec */ 34 #define T_RTP_TCK (BL / 2) 35 #define T_XP_TCK 2 /* clocks */ 36 #define T_CKE_TCK 3 /* clocks */ 37 #define T_XSNR (T_RFC_MIN + 10000) /* psec */ 38 #define T_DLLK 200 /* clocks */ 39 #define T_RAS_MIN 45000 /* psec */ 40 #define T_RC 57500 /* psec */ 41 #define T_FAW 35000 /* psec */ 42 #define T_MRD_TCK 2 /* clocks */ 43 #define T_RFI 7800000 /* psec */ 44 45 /* DDR Addressing */ 46 #define COL_BITS 10 47 #define BA_BITS 3 48 #define ROW_BITS 13 49 #define CS_BITS 1 50 51 /* DDR Addressing scheme: {CS, ROW, BA, COL} */ 52 #define COL_HI_RSHFT 0 53 #define COL_HI_MASK 0 54 #define COL_LO_MASK ((1 << COL_BITS) - 1) 55 56 #define BA_RSHFT COL_BITS 57 #define BA_MASK ((1 << BA_BITS) - 1) 58 59 #define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS) 60 #define ROW_ADDR_MASK ((1 << ROW_BITS) - 1) 61 62 #define CS_ADDR_RSHIFT 0 63 #define CS_ADDR_MASK 0 64 65 #endif /* __MICROCHIP_DDR2_TIMING_H */ 66