1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
4  *
5  */
6 
7 #ifndef __MICROCHIP_DDR2_REGS_H
8 #define __MICROCHIP_DDR2_REGS_H
9 
10 #include <linux/bitops.h>
11 
12 /* DDR2 Controller */
13 struct ddr2_ctrl_regs {
14 	u32 tsel;
15 	u32 minlim;
16 	u32 reqprd;
17 	u32 mincmd;
18 	u32 memcon;
19 	u32 memcfg0;
20 	u32 memcfg1;
21 	u32 memcfg2;
22 	u32 memcfg3;
23 	u32 memcfg4;
24 	u32 refcfg;
25 	u32 pwrcfg;
26 	u32 dlycfg0;
27 	u32 dlycfg1;
28 	u32 dlycfg2;
29 	u32 dlycfg3;
30 	u32 odtcfg;
31 	u32 xfercfg;
32 	u32 cmdissue;
33 	u32 odtencfg;
34 	u32 memwidth;
35 	u32 unused[11];
36 	u32 cmd10[16];
37 	u32 cmd20[16];
38 };
39 
40 /* Arbiter Config */
41 #define MIN_LIM_WIDTH		5
42 #define RQST_PERIOD_WIDTH	8
43 #define MIN_CMDACPT_WIDTH	8
44 
45 /* Refresh Config */
46 #define REFCNT_CLK(x)		(x)
47 #define REFDLY_CLK(x)		((x) << 16)
48 #define MAX_PEND_REF(x)		((x) << 24)
49 
50 /* Power Config */
51 #define PRECH_PWR_DN_ONLY(x)	((x) << 22)
52 #define SELF_REF_DLY(x)		((x) << 12)
53 #define PWR_DN_DLY(x)		((x) << 4)
54 #define EN_AUTO_SELF_REF(x)	((x) << 3)
55 #define EN_AUTO_PWR_DN(x)	((x) << 2)
56 #define ERR_CORR_EN(x)		((x) << 1)
57 #define ECC_EN(x)		(x)
58 
59 /* Memory Width */
60 #define HALF_RATE_MODE		BIT(3)
61 
62 /* Delay Config */
63 #define ODTWLEN(x)	((x) << 20)
64 #define ODTRLEN(x)	((x) << 16)
65 #define ODTWDLY(x)	((x) << 12)
66 #define ODTRDLY(x)	((x) << 8)
67 
68 /* Xfer Config */
69 #define BIG_ENDIAN(x)	((x) << 31)
70 #define MAX_BURST(x)	((x) << 24)
71 #define RDATENDLY(x)	((x) << 16)
72 #define NXDATAVDLY(x)	((x) << 4)
73 #define NXTDATRQDLY(x)	((x) << 0)
74 
75 /* Host Commands */
76 #define IDLE_NOP	0x00ffffff
77 #define PRECH_ALL_CMD	0x00fff401
78 #define REF_CMD		0x00fff801
79 #define LOAD_MODE_CMD	0x00fff001
80 #define CKE_LOW		0x00ffeffe
81 
82 #define NUM_HOST_CMDS	12
83 
84 /* Host CMD Issue */
85 #define CMD_VALID	BIT(4)
86 #define NUMHOSTCMD(x)	(x)
87 
88 /* Memory Control */
89 #define INIT_DONE	BIT(1)
90 #define INIT_START	BIT(0)
91 
92 /* Address Control */
93 #define EN_AUTO_PRECH		0
94 #define SB_PRI			1
95 
96 /* DDR2 Phy Register */
97 struct ddr2_phy_regs {
98 	u32 scl_start;
99 	u32 unused1[2];
100 	u32 scl_latency;
101 	u32 unused2[2];
102 	u32 scl_config_1;
103 	u32 scl_config_2;
104 	u32 pad_ctrl;
105 	u32 dll_recalib;
106 };
107 
108 /* PHY PAD CONTROL */
109 #define ODT_SEL			BIT(0)
110 #define ODT_EN			BIT(1)
111 #define DRIVE_SEL(x)		((x) << 2)
112 #define ODT_PULLDOWN(x)		((x) << 4)
113 #define ODT_PULLUP(x)		((x) << 6)
114 #define EXTRA_OEN_CLK(x)	((x) << 8)
115 #define NOEXT_DLL		BIT(9)
116 #define DLR_DFT_WRCMD		BIT(13)
117 #define HALF_RATE		BIT(14)
118 #define DRVSTR_PFET(x)		((x) << 16)
119 #define DRVSTR_NFET(x)		((x) << 20)
120 #define RCVR_EN			BIT(28)
121 #define PREAMBLE_DLY(x)		((x) << 29)
122 
123 /* PHY DLL RECALIBRATE */
124 #define RECALIB_CNT(x)		((x) << 8)
125 #define DISABLE_RECALIB(x)	((x) << 26)
126 #define DELAY_START_VAL(x)	((x) << 28)
127 
128 /* PHY SCL CONFIG1 */
129 #define SCL_BURST8		BIT(0)
130 #define SCL_DDR_CONNECTED		BIT(1)
131 #define SCL_RCAS_LAT(x)		((x) << 4)
132 #define SCL_ODTCSWW		BIT(24)
133 
134 /* PHY SCL CONFIG2 */
135 #define SCL_CSEN		BIT(0)
136 #define SCL_WCAS_LAT(x)		((x) << 8)
137 
138 /* PHY SCL Latency */
139 #define SCL_CAPCLKDLY(x)	((x) << 0)
140 #define SCL_DDRCLKDLY(x)	((x) << 4)
141 
142 /* PHY SCL START */
143 #define SCL_START		BIT(28)
144 #define SCL_EN			BIT(26)
145 #define SCL_LUBPASS		(BIT(1) | BIT(0))
146 
147 #endif	/* __MICROCHIP_DDR2_REGS_H */
148