1 /* 2 * (c) 2015 Paul Thacker <paul.thacker@microchip.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 */ 7 #include <common.h> 8 #include <wait_bit.h> 9 #include <linux/kernel.h> 10 #include <linux/bitops.h> 11 #include <mach/pic32.h> 12 #include <mach/ddr.h> 13 14 #include "ddr2_regs.h" 15 #include "ddr2_timing.h" 16 17 /* init DDR2 Phy */ 18 void ddr2_phy_init(void) 19 { 20 struct ddr2_phy_regs *ddr2_phy; 21 u32 pad_ctl; 22 23 ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); 24 25 /* PHY_DLL_RECALIB */ 26 writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) | 27 RECALIB_CNT(0x10), &ddr2_phy->dll_recalib); 28 29 /* PHY_PAD_CTRL */ 30 pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) | 31 ODT_PULLDOWN(2) | ODT_PULLUP(3) | 32 EXTRA_OEN_CLK(0) | NOEXT_DLL | 33 DLR_DFT_WRCMD | HALF_RATE | 34 DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) | 35 RCVR_EN | PREAMBLE_DLY(2); 36 writel(pad_ctl, &ddr2_phy->pad_ctrl); 37 38 /* SCL_CONFIG_0 */ 39 writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) | 40 SCL_ODTCSWW, &ddr2_phy->scl_config_1); 41 42 /* SCL_CONFIG_1 */ 43 writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2); 44 45 /* SCL_LAT */ 46 writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency); 47 } 48 49 /* start phy self calibration logic */ 50 static int ddr2_phy_calib_start(void) 51 { 52 struct ddr2_phy_regs *ddr2_phy; 53 54 ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy)); 55 56 /* DDR Phy SCL Start */ 57 writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); 58 59 /* Wait for SCL for data byte to pass */ 60 return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS, 61 true, CONFIG_SYS_HZ, false); 62 } 63 64 /* DDR2 Controller initialization */ 65 66 /* Target Agent Arbiter */ 67 static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, 68 const struct ddr2_arbiter_params *const param) 69 { 70 int i; 71 72 for (i = 0; i < NUM_AGENTS; i++) { 73 /* set min burst size */ 74 writel(i * MIN_LIM_WIDTH, &ctrl->tsel); 75 writel(param->min_limit, &ctrl->minlim); 76 77 /* set request period (4 * req_period clocks) */ 78 writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); 79 writel(param->req_period, &ctrl->reqprd); 80 81 /* set number of burst accepted */ 82 writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); 83 writel(param->min_cmd_acpt, &ctrl->mincmd); 84 } 85 } 86 87 const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void) 88 { 89 /* default arbiter parameters */ 90 static const struct ddr2_arbiter_params arb_params[] = { 91 { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x04,}, 92 { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, 93 { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,}, 94 { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, 95 { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,}, 96 }; 97 98 return &arb_params[0]; 99 } 100 101 static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, 102 u32 hostcmd2, u32 hostcmd1, u32 delay) 103 { 104 u32 hc_delay; 105 106 hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; 107 writel(hostcmd1, &ctrl->cmd10[cmd_idx]); 108 writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); 109 } 110 111 /* init DDR2 Controller */ 112 void ddr2_ctrl_init(void) 113 { 114 u32 wr2prech, rd2prech, wr2rd, wr2rd_cs; 115 u32 ras2ras, ras2cas, prech2ras, temp; 116 const struct ddr2_arbiter_params *arb_params; 117 struct ddr2_ctrl_regs *ctrl; 118 119 ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); 120 121 /* PIC32 DDR2 controller always work in HALF_RATE */ 122 writel(HALF_RATE_MODE, &ctrl->memwidth); 123 124 /* Set arbiter configuration per target */ 125 arb_params = board_get_ddr_arbiter_params(); 126 ddr_set_arbiter(ctrl, arb_params); 127 128 /* Address Configuration, model {CS, ROW, BA, COL} */ 129 writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) | 130 (COL_HI_RSHFT << 24) | (SB_PRI << 29) | 131 (EN_AUTO_PRECH << 30)), &ctrl->memcfg0); 132 133 writel(ROW_ADDR_MASK, &ctrl->memcfg1); 134 writel(COL_HI_MASK, &ctrl->memcfg2); 135 writel(COL_LO_MASK, &ctrl->memcfg3); 136 writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4); 137 138 /* Refresh Config */ 139 writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | 140 REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | 141 MAX_PEND_REF(7), 142 &ctrl->refcfg); 143 144 /* Power Config */ 145 writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) | 146 EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) | 147 SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0), 148 &ctrl->pwrcfg); 149 150 /* Delay Config */ 151 wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), 152 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; 153 wr2rd_cs = max_t(u32, wr2rd - 1, 3); 154 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; 155 rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), 156 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; 157 ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), 158 DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; 159 ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1; 160 prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1; 161 162 writel(((wr2rd & 0x0f) | 163 ((wr2rd_cs & 0x0f) << 4) | 164 ((BL - 1) << 8) | 165 (BL << 12) | 166 ((BL - 1) << 16) | 167 ((BL - 1) << 20) | 168 ((BL + 2) << 24) | 169 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); 170 171 writel(((T_CKE_TCK - 1) | 172 (((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) | 173 ((T_CKE_TCK - 1) << 16) | 174 ((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) | 175 ((wr2prech >> 4) << 26) | 176 ((wr2rd >> 4) << 27) | 177 ((wr2rd_cs >> 4) << 28) | 178 (((RL + 5) >> 4) << 29) | 179 ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1); 180 181 writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) | 182 (rd2prech << 8) | 183 ((wr2prech & 0x0f) << 12) | 184 (ras2ras << 16) | 185 (ras2cas << 20) | 186 (prech2ras << 24) | 187 ((RL + 3) << 28)), &ctrl->dlycfg2); 188 189 writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) | 190 ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) | 191 ((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)), 192 &ctrl->dlycfg3); 193 194 /* ODT Config */ 195 writel(0x0, &ctrl->odtcfg); 196 writel(BIT(16), &ctrl->odtencfg); 197 writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3), 198 &ctrl->odtcfg); 199 200 /* Transfer Configuration */ 201 writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) | 202 MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0), 203 &ctrl->xfercfg); 204 205 /* DRAM Initialization */ 206 /* CKE high after reset and wait 400 nsec */ 207 host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000); 208 209 /* issue precharge all command */ 210 host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK); 211 212 /* initialize EMR2 */ 213 host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK); 214 215 /* initialize EMR3 */ 216 host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK); 217 218 /* 219 * RDQS disable, DQSB enable, OCD exit, 150 ohm termination, 220 * AL=0, DLL enable 221 */ 222 host_load_cmd(ctrl, 4, 0x100, 223 LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK * T_CK); 224 /* 225 * PD fast exit, WR REC = T_WR in clocks -1, 226 * DLL reset, CAS = RL, burst = 4 227 */ 228 temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1; 229 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), 230 T_MRD_TCK * T_CK); 231 232 /* issue precharge all command */ 233 host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK); 234 235 /* issue refresh command */ 236 host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN); 237 238 /* issue refresh command */ 239 host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN); 240 241 /* Mode register programming as before without DLL reset */ 242 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), 243 T_MRD_TCK * T_CK); 244 245 /* extended mode register same as before with OCD default */ 246 host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24), 247 T_MRD_TCK * T_CK); 248 249 /* extended mode register same as before with OCD exit */ 250 host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28), 251 140 * T_CK); 252 253 writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue); 254 255 /* start memory initialization */ 256 writel(INIT_START, &ctrl->memcon); 257 258 /* wait for all host cmds to be transmitted */ 259 wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false, 260 CONFIG_SYS_HZ, false); 261 262 /* inform all cmds issued, ready for normal operation */ 263 writel(INIT_START | INIT_DONE, &ctrl->memcon); 264 265 /* perform phy caliberation */ 266 if (ddr2_phy_calib_start()) 267 printf("ddr2: phy calib failed\n"); 268 } 269 270 phys_size_t ddr2_calculate_size(void) 271 { 272 u32 temp; 273 274 temp = 1 << (COL_BITS + BA_BITS + ROW_BITS); 275 /* 16-bit data width between controller and DIMM */ 276 temp = temp * CS_BITS * (16 / 8); 277 return (phys_size_t)temp; 278 } 279