1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __XOR_REGS_H 8 #define __XOR_REGS_H 9 10 /* 11 * For controllers that have two XOR units, then chans 2 & 3 will be mapped 12 * to channels 0 & 1 of unit 1 13 */ 14 #define XOR_UNIT(chan) ((chan) >> 1) 15 #define XOR_CHAN(chan) ((chan) & 1) 16 17 #define MV_XOR_REGS_OFFSET(unit) (0x60900) 18 #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) 19 20 /* XOR Engine Control Register Map */ 21 #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) 22 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) 23 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) 24 25 /* XOR Engine Interrupt Register Map */ 26 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x30) 27 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x40) 28 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x50) 29 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x60) 30 31 /* XOR Engine Descriptor Register Map */ 32 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) 33 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) 34 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) 35 36 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) 37 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) 38 #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D0) 39 #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D4) 40 #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2D8) 41 #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E0) 42 #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + 0x2E4) 43 44 /* XOR register fileds */ 45 46 /* XOR Engine [0..1] Configuration Registers (XExCR) */ 47 #define XEXCR_OPERATION_MODE_OFFS (0) 48 #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) 49 #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) 50 #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) 51 #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) 52 #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) 53 #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) 54 55 #define XEXCR_SRC_BURST_LIMIT_OFFS (4) 56 #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) 57 #define XEXCR_DST_BURST_LIMIT_OFFS (8) 58 #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) 59 #define XEXCR_DRD_RES_SWP_OFFS (12) 60 #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) 61 #define XEXCR_DWR_REQ_SWP_OFFS (13) 62 #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) 63 #define XEXCR_DES_SWP_OFFS (14) 64 #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) 65 #define XEXCR_REG_ACC_PROTECT_OFFS (15) 66 #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) 67 68 /* XOR Engine [0..1] Activation Registers (XExACTR) */ 69 #define XEXACTR_XESTART_OFFS (0) 70 #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) 71 #define XEXACTR_XESTOP_OFFS (1) 72 #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) 73 #define XEXACTR_XEPAUSE_OFFS (2) 74 #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) 75 #define XEXACTR_XERESTART_OFFS (3) 76 #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) 77 #define XEXACTR_XESTATUS_OFFS (4) 78 #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) 79 #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) 80 #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) 81 #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) 82 83 /* XOR Engine [0..1] Destination Pointer Register (XExDPR0) */ 84 #define XEXDPR_DST_PTR_OFFS (0) 85 #define XEXDPR_DST_PTR_MASK (0xFFFFFFFF << XEXDPR_DST_PTR_OFFS) 86 #define XEXDPR_DST_PTR_XOR_MASK (0x3F) 87 #define XEXDPR_DST_PTR_DMA_MASK (0x1F) 88 #define XEXDPR_DST_PTR_CRC_MASK (0x1F) 89 90 /* XOR Engine[0..1] Block Size Registers (XExBSR) */ 91 #define XEXBSR_BLOCK_SIZE_OFFS (0) 92 #define XEXBSR_BLOCK_SIZE_MASK (0xFFFFFFFF << XEXBSR_BLOCK_SIZE_OFFS) 93 #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) 94 #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xFFFFFFFF) 95 96 /* XOR Engine Address Decoding Register Map */ 97 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) 98 #define XOR_BASE_ADDR_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x250 + ((win) * 4))) 99 #define XOR_SIZE_MASK_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x270 + ((win) * 4))) 100 #define XOR_HIGH_ADDR_REMAP_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x290 + ((win) * 4))) 101 #define XOR_ADDR_OVRD_REG(unit, win) (MV_XOR_REGS_BASE(unit) + (0x2A0 + ((win) * 4))) 102 103 #endif /* __XOR_REGS_H */ 104