1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef __DDR3_INIT_H
7 #define __DDR3_INIT_H
8 
9 /*
10  * Debug
11  */
12 
13 /*
14  * MV_DEBUG_INIT need to be defines, otherwise the output of the
15  * DDR2 training code is not complete and misleading
16  */
17 #define MV_DEBUG_INIT
18 
19 #ifdef MV_DEBUG_INIT
20 #define DEBUG_INIT_S(s)			puts(s)
21 #define DEBUG_INIT_D(d, l)		printf("%x", d)
22 #define DEBUG_INIT_D_10(d, l)		printf("%d", d)
23 #else
24 #define DEBUG_INIT_S(s)
25 #define DEBUG_INIT_D(d, l)
26 #define DEBUG_INIT_D_10(d, l)
27 #endif
28 
29 #ifdef MV_DEBUG_INIT_FULL
30 #define DEBUG_INIT_FULL_S(s)		puts(s)
31 #define DEBUG_INIT_FULL_D(d, l)		printf("%x", d)
32 #define DEBUG_INIT_FULL_D_10(d, l)	printf("%d", d)
33 #define DEBUG_WR_REG(reg, val) \
34 	{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
35 	  DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
36 #define DEBUG_RD_REG(reg, val) \
37 	{ DEBUG_INIT_S("Read  Reg: 0x"); DEBUG_INIT_D((reg), 8); \
38 	  DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
39 #else
40 #define DEBUG_INIT_FULL_S(s)
41 #define DEBUG_INIT_FULL_D(d, l)
42 #define DEBUG_INIT_FULL_D_10(d, l)
43 #define DEBUG_WR_REG(reg, val)
44 #define DEBUG_RD_REG(reg, val)
45 #endif
46 
47 #define DEBUG_INIT_FULL_C(s, d, l) \
48 	{ DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
49 #define DEBUG_INIT_C(s, d, l) \
50 	{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
51 
52 #define MV_MBUS_REGS_OFFSET                 (0x20000)
53 
54 #include "ddr3_hw_training.h"
55 
56 #define MAX_DIMM_NUM			2
57 #define SPD_SIZE			128
58 
59 #ifdef MV88F78X60
60 #include "ddr3_axp.h"
61 #elif defined(MV88F67XX)
62 #include "ddr3_a370.h"
63 #elif defined(MV88F672X)
64 #include "ddr3_a375.h"
65 #endif
66 
67 /* DRR training Error codes */
68 /* Stage 0 errors */
69 #define MV_DDR3_TRAINING_ERR_BAD_SAR			0xDD300001
70 /* Stage 1 errors */
71 #define MV_DDR3_TRAINING_ERR_TWSI_FAIL			0xDD301001
72 #define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH		0xDD301001
73 #define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE		0xDD301003
74 #define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH	0xDD301004
75 #define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP		0xDD301005
76 #define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT		0xDD301006
77 #define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT		0xDD301007
78 #define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP		0xDD301008
79 /* Stage 2 errors */
80 #define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE		0xDD302000
81 
82 typedef enum config_type {
83 	CONFIG_ECC,
84 	CONFIG_MULTI_CS,
85 	CONFIG_BUS_WIDTH
86 } MV_CONFIG_TYPE;
87 
88 enum log_level  {
89 	MV_LOG_LEVEL_0,
90 	MV_LOG_LEVEL_1,
91 	MV_LOG_LEVEL_2,
92 	MV_LOG_LEVEL_3
93 };
94 
95 int ddr3_hw_training(u32 target_freq, u32 ddr_width,
96 		     int xor_bypass, u32 scrub_offs, u32 scrub_size,
97 		     int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl);
98 
99 void ddr3_print_version(void);
100 void fix_pll_val(u8 target_fab);
101 u8 ddr3_get_eprom_fabric(void);
102 u32 ddr3_get_fab_opt(void);
103 u32 ddr3_get_cpu_freq(void);
104 u32 ddr3_get_vco_freq(void);
105 int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
106 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
107 			     u32 mask2);
108 u32 ddr3_cl_to_valid_cl(u32 cl);
109 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
110 u32 ddr3_get_cs_num_from_reg(void);
111 u32 ddr3_get_cs_ena_from_reg(void);
112 u8 mv_ctrl_rev_get(void);
113 
114 u32 ddr3_get_log_level(void);
115 
116 /* SPD */
117 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
118 
119 /*
120  * Accessor functions for the registers
121  */
122 static inline void reg_write(u32 addr, u32 val)
123 {
124 	writel(val, INTER_REGS_BASE + addr);
125 }
126 
127 static inline u32 reg_read(u32 addr)
128 {
129 	return readl(INTER_REGS_BASE + addr);
130 }
131 
132 static inline void reg_bit_set(u32 addr, u32 mask)
133 {
134 	setbits_le32(INTER_REGS_BASE + addr, mask);
135 }
136 
137 static inline void reg_bit_clr(u32 addr, u32 mask)
138 {
139 	clrbits_le32(INTER_REGS_BASE + addr, mask);
140 }
141 
142 #endif /* __DDR3_INIT_H */
143