1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __DDR3_INIT_H 8 #define __DDR3_INIT_H 9 10 /* 11 * Debug 12 */ 13 14 /* 15 * MV_DEBUG_INIT need to be defines, otherwise the output of the 16 * DDR2 training code is not complete and misleading 17 */ 18 #define MV_DEBUG_INIT 19 20 #ifdef MV_DEBUG_INIT 21 #define DEBUG_INIT_S(s) puts(s) 22 #define DEBUG_INIT_D(d, l) printf("%x", d) 23 #define DEBUG_INIT_D_10(d, l) printf("%d", d) 24 #else 25 #define DEBUG_INIT_S(s) 26 #define DEBUG_INIT_D(d, l) 27 #define DEBUG_INIT_D_10(d, l) 28 #endif 29 30 #ifdef MV_DEBUG_INIT_FULL 31 #define DEBUG_INIT_FULL_S(s) puts(s) 32 #define DEBUG_INIT_FULL_D(d, l) printf("%x", d) 33 #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d) 34 #define DEBUG_WR_REG(reg, val) \ 35 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \ 36 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); } 37 #define DEBUG_RD_REG(reg, val) \ 38 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \ 39 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); } 40 #else 41 #define DEBUG_INIT_FULL_S(s) 42 #define DEBUG_INIT_FULL_D(d, l) 43 #define DEBUG_INIT_FULL_D_10(d, l) 44 #define DEBUG_WR_REG(reg, val) 45 #define DEBUG_RD_REG(reg, val) 46 #endif 47 48 #define DEBUG_INIT_FULL_C(s, d, l) \ 49 { DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); } 50 #define DEBUG_INIT_C(s, d, l) \ 51 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); } 52 53 #define MV_MBUS_REGS_OFFSET (0x20000) 54 55 #include "ddr3_hw_training.h" 56 57 #define MAX_DIMM_NUM 2 58 #define SPD_SIZE 128 59 60 #ifdef MV88F78X60 61 #include "ddr3_axp.h" 62 #elif defined(MV88F67XX) 63 #include "ddr3_a370.h" 64 #elif defined(MV88F672X) 65 #include "ddr3_a375.h" 66 #endif 67 68 /* DRR training Error codes */ 69 /* Stage 0 errors */ 70 #define MV_DDR3_TRAINING_ERR_BAD_SAR 0xDD300001 71 /* Stage 1 errors */ 72 #define MV_DDR3_TRAINING_ERR_TWSI_FAIL 0xDD301001 73 #define MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH 0xDD301001 74 #define MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE 0xDD301003 75 #define MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH 0xDD301004 76 #define MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP 0xDD301005 77 #define MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT 0xDD301006 78 #define MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT 0xDD301007 79 #define MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP 0xDD301008 80 /* Stage 2 errors */ 81 #define MV_DDR3_TRAINING_ERR_HW_FAIL_BASE 0xDD302000 82 83 typedef enum config_type { 84 CONFIG_ECC, 85 CONFIG_MULTI_CS, 86 CONFIG_BUS_WIDTH 87 } MV_CONFIG_TYPE; 88 89 enum log_level { 90 MV_LOG_LEVEL_0, 91 MV_LOG_LEVEL_1, 92 MV_LOG_LEVEL_2, 93 MV_LOG_LEVEL_3 94 }; 95 96 int ddr3_hw_training(u32 target_freq, u32 ddr_width, 97 int xor_bypass, u32 scrub_offs, u32 scrub_size, 98 int dqs_clk_aligned, int debug_mode, int reg_dimm_skip_wl); 99 100 void ddr3_print_version(void); 101 void fix_pll_val(u8 target_fab); 102 u8 ddr3_get_eprom_fabric(void); 103 u32 ddr3_get_fab_opt(void); 104 u32 ddr3_get_cpu_freq(void); 105 u32 ddr3_get_vco_freq(void); 106 int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type); 107 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2, 108 u32 mask2); 109 u32 ddr3_cl_to_valid_cl(u32 cl); 110 u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl); 111 u32 ddr3_get_cs_num_from_reg(void); 112 u32 ddr3_get_cs_ena_from_reg(void); 113 u8 mv_ctrl_rev_get(void); 114 115 u32 ddr3_get_log_level(void); 116 117 /* SPD */ 118 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width); 119 120 /* 121 * Accessor functions for the registers 122 */ 123 static inline void reg_write(u32 addr, u32 val) 124 { 125 writel(val, INTER_REGS_BASE + addr); 126 } 127 128 static inline u32 reg_read(u32 addr) 129 { 130 return readl(INTER_REGS_BASE + addr); 131 } 132 133 static inline void reg_bit_set(u32 addr, u32 mask) 134 { 135 setbits_le32(INTER_REGS_BASE + addr, mask); 136 } 137 138 static inline void reg_bit_clr(u32 addr, u32 mask) 139 { 140 clrbits_le32(INTER_REGS_BASE + addr, mask); 141 } 142 143 #endif /* __DDR3_INIT_H */ 144