1*ff9112dfSStefan Roese /* 2*ff9112dfSStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*ff9112dfSStefan Roese * 4*ff9112dfSStefan Roese * SPDX-License-Identifier: GPL-2.0 5*ff9112dfSStefan Roese */ 6*ff9112dfSStefan Roese 7*ff9112dfSStefan Roese #ifndef __AXP_TRAINING_STATIC_H 8*ff9112dfSStefan Roese #define __AXP_TRAINING_STATIC_H 9*ff9112dfSStefan Roese 10*ff9112dfSStefan Roese /* 11*ff9112dfSStefan Roese * STATIC_TRAINING - Set only if static parameters for training are set and 12*ff9112dfSStefan Roese * required 13*ff9112dfSStefan Roese */ 14*ff9112dfSStefan Roese 15*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = { 16*ff9112dfSStefan Roese /* Read Leveling */ 17*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 18*ff9112dfSStefan Roese /*0 */ 19*ff9112dfSStefan Roese {0x000016A0, 0xC002011A}, 20*ff9112dfSStefan Roese /*1 */ 21*ff9112dfSStefan Roese {0x000016A0, 0xC0420100}, 22*ff9112dfSStefan Roese /*2 */ 23*ff9112dfSStefan Roese {0x000016A0, 0xC082020A}, 24*ff9112dfSStefan Roese /*3 */ 25*ff9112dfSStefan Roese {0x000016A0, 0xC0C20017}, 26*ff9112dfSStefan Roese /*4 */ 27*ff9112dfSStefan Roese {0x000016A0, 0xC1020113}, 28*ff9112dfSStefan Roese /*5 */ 29*ff9112dfSStefan Roese {0x000016A0, 0xC1420107}, 30*ff9112dfSStefan Roese /*6 */ 31*ff9112dfSStefan Roese {0x000016A0, 0xC182011F}, 32*ff9112dfSStefan Roese /*7 */ 33*ff9112dfSStefan Roese {0x000016A0, 0xC1C2001C}, 34*ff9112dfSStefan Roese /*8 */ 35*ff9112dfSStefan Roese {0x000016A0, 0xC202010D}, 36*ff9112dfSStefan Roese 37*ff9112dfSStefan Roese /* Write Leveling */ 38*ff9112dfSStefan Roese /*0 */ 39*ff9112dfSStefan Roese {0x000016A0, 0xC0004A06}, 40*ff9112dfSStefan Roese /*1 */ 41*ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 42*ff9112dfSStefan Roese /*2 */ 43*ff9112dfSStefan Roese {0x000016A0, 0xC0806A0D}, 44*ff9112dfSStefan Roese /*3 */ 45*ff9112dfSStefan Roese {0x000016A0, 0xC0C0A01B}, 46*ff9112dfSStefan Roese /*4 */ 47*ff9112dfSStefan Roese {0x000016A0, 0xC1003A01}, 48*ff9112dfSStefan Roese /*5 */ 49*ff9112dfSStefan Roese {0x000016A0, 0xC1408113}, 50*ff9112dfSStefan Roese /*6 */ 51*ff9112dfSStefan Roese {0x000016A0, 0xC1805609}, 52*ff9112dfSStefan Roese /*7 */ 53*ff9112dfSStefan Roese {0x000016A0, 0xC1C04504}, 54*ff9112dfSStefan Roese /*8 */ 55*ff9112dfSStefan Roese {0x000016A0, 0xC2009518}, 56*ff9112dfSStefan Roese 57*ff9112dfSStefan Roese /*center DQS on read cycle */ 58*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 59*ff9112dfSStefan Roese 60*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 61*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 62*ff9112dfSStefan Roese 63*ff9112dfSStefan Roese /*init DRAM */ 64*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 65*ff9112dfSStefan Roese {0x0, 0x0} 66*ff9112dfSStefan Roese }; 67*ff9112dfSStefan Roese 68*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = { 69*ff9112dfSStefan Roese /* Read Leveling */ 70*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 71*ff9112dfSStefan Roese /*0 */ 72*ff9112dfSStefan Roese {0x000016A0, 0xC0020301}, 73*ff9112dfSStefan Roese /*1 */ 74*ff9112dfSStefan Roese {0x000016A0, 0xC0420202}, 75*ff9112dfSStefan Roese /*2 */ 76*ff9112dfSStefan Roese {0x000016A0, 0xC0820314}, 77*ff9112dfSStefan Roese /*3 */ 78*ff9112dfSStefan Roese {0x000016A0, 0xC0C20117}, 79*ff9112dfSStefan Roese /*4 */ 80*ff9112dfSStefan Roese {0x000016A0, 0xC1020219}, 81*ff9112dfSStefan Roese /*5 */ 82*ff9112dfSStefan Roese {0x000016A0, 0xC142020B}, 83*ff9112dfSStefan Roese /*6 */ 84*ff9112dfSStefan Roese {0x000016A0, 0xC182030A}, 85*ff9112dfSStefan Roese /*7 */ 86*ff9112dfSStefan Roese {0x000016A0, 0xC1C2011D}, 87*ff9112dfSStefan Roese /*8 */ 88*ff9112dfSStefan Roese {0x000016A0, 0xC2020212}, 89*ff9112dfSStefan Roese 90*ff9112dfSStefan Roese /* Write Leveling */ 91*ff9112dfSStefan Roese /*0 */ 92*ff9112dfSStefan Roese {0x000016A0, 0xC0007A12}, 93*ff9112dfSStefan Roese /*1 */ 94*ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 95*ff9112dfSStefan Roese /*2 */ 96*ff9112dfSStefan Roese {0x000016A0, 0xC0809E1B}, 97*ff9112dfSStefan Roese /*3 */ 98*ff9112dfSStefan Roese {0x000016A0, 0xC0C0AC1F}, 99*ff9112dfSStefan Roese /*4 */ 100*ff9112dfSStefan Roese {0x000016A0, 0xC1005E0A}, 101*ff9112dfSStefan Roese /*5 */ 102*ff9112dfSStefan Roese {0x000016A0, 0xC140A91D}, 103*ff9112dfSStefan Roese /*6 */ 104*ff9112dfSStefan Roese {0x000016A0, 0xC1808E17}, 105*ff9112dfSStefan Roese /*7 */ 106*ff9112dfSStefan Roese {0x000016A0, 0xC1C05509}, 107*ff9112dfSStefan Roese /*8 */ 108*ff9112dfSStefan Roese {0x000016A0, 0xC2003A01}, 109*ff9112dfSStefan Roese 110*ff9112dfSStefan Roese /* PBS Leveling */ 111*ff9112dfSStefan Roese /*0 */ 112*ff9112dfSStefan Roese {0x000016A0, 0xC0007A12}, 113*ff9112dfSStefan Roese /*1 */ 114*ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 115*ff9112dfSStefan Roese /*2 */ 116*ff9112dfSStefan Roese {0x000016A0, 0xC0809E1B}, 117*ff9112dfSStefan Roese /*3 */ 118*ff9112dfSStefan Roese {0x000016A0, 0xC0C0AC1F}, 119*ff9112dfSStefan Roese /*4 */ 120*ff9112dfSStefan Roese {0x000016A0, 0xC1005E0A}, 121*ff9112dfSStefan Roese /*5 */ 122*ff9112dfSStefan Roese {0x000016A0, 0xC140A91D}, 123*ff9112dfSStefan Roese /*6 */ 124*ff9112dfSStefan Roese {0x000016A0, 0xC1808E17}, 125*ff9112dfSStefan Roese /*7 */ 126*ff9112dfSStefan Roese {0x000016A0, 0xC1C05509}, 127*ff9112dfSStefan Roese /*8 */ 128*ff9112dfSStefan Roese {0x000016A0, 0xC2003A01}, 129*ff9112dfSStefan Roese 130*ff9112dfSStefan Roese /*center DQS on read cycle */ 131*ff9112dfSStefan Roese {0x000016A0, 0xC803000B}, 132*ff9112dfSStefan Roese 133*ff9112dfSStefan Roese {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */ 134*ff9112dfSStefan Roese {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */ 135*ff9112dfSStefan Roese 136*ff9112dfSStefan Roese /*init DRAM */ 137*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 138*ff9112dfSStefan Roese {0x0, 0x0} 139*ff9112dfSStefan Roese }; 140*ff9112dfSStefan Roese 141*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = { 142*ff9112dfSStefan Roese /* Read Leveling */ 143*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 144*ff9112dfSStefan Roese /*0 2 4 15 */ 145*ff9112dfSStefan Roese {0x000016A0, 0xC002010C}, 146*ff9112dfSStefan Roese /*1 2 4 2 */ 147*ff9112dfSStefan Roese {0x000016A0, 0xC042001C}, 148*ff9112dfSStefan Roese /*2 2 4 27 */ 149*ff9112dfSStefan Roese {0x000016A0, 0xC0820115}, 150*ff9112dfSStefan Roese /*3 2 4 0 */ 151*ff9112dfSStefan Roese {0x000016A0, 0xC0C20019}, 152*ff9112dfSStefan Roese /*4 2 4 13 */ 153*ff9112dfSStefan Roese {0x000016A0, 0xC1020108}, 154*ff9112dfSStefan Roese /*5 2 4 5 */ 155*ff9112dfSStefan Roese {0x000016A0, 0xC1420100}, 156*ff9112dfSStefan Roese /*6 2 4 19 */ 157*ff9112dfSStefan Roese {0x000016A0, 0xC1820111}, 158*ff9112dfSStefan Roese /*7 2 4 0 */ 159*ff9112dfSStefan Roese {0x000016A0, 0xC1C2001B}, 160*ff9112dfSStefan Roese /*8 2 4 10 */ 161*ff9112dfSStefan Roese /*{0x000016A0, 0xC2020117}, */ 162*ff9112dfSStefan Roese {0x000016A0, 0xC202010C}, 163*ff9112dfSStefan Roese 164*ff9112dfSStefan Roese /* Write Leveling */ 165*ff9112dfSStefan Roese /*0 */ 166*ff9112dfSStefan Roese {0x000016A0, 0xC0005508}, 167*ff9112dfSStefan Roese /*1 */ 168*ff9112dfSStefan Roese {0x000016A0, 0xC0409819}, 169*ff9112dfSStefan Roese /*2 */ 170*ff9112dfSStefan Roese {0x000016A0, 0xC080650C}, 171*ff9112dfSStefan Roese /*3 */ 172*ff9112dfSStefan Roese {0x000016A0, 0xC0C0700F}, 173*ff9112dfSStefan Roese /*4 */ 174*ff9112dfSStefan Roese {0x000016A0, 0xC1004103}, 175*ff9112dfSStefan Roese /*5 */ 176*ff9112dfSStefan Roese {0x000016A0, 0xC140A81D}, 177*ff9112dfSStefan Roese /*6 */ 178*ff9112dfSStefan Roese {0x000016A0, 0xC180650C}, 179*ff9112dfSStefan Roese /*7 */ 180*ff9112dfSStefan Roese {0x000016A0, 0xC1C08013}, 181*ff9112dfSStefan Roese /*8 */ 182*ff9112dfSStefan Roese {0x000016A0, 0xC2005508}, 183*ff9112dfSStefan Roese 184*ff9112dfSStefan Roese /*center DQS on read cycle */ 185*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 186*ff9112dfSStefan Roese 187*ff9112dfSStefan Roese {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ 188*ff9112dfSStefan Roese {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ 189*ff9112dfSStefan Roese 190*ff9112dfSStefan Roese /*init DRAM */ 191*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 192*ff9112dfSStefan Roese {0x0, 0x0} 193*ff9112dfSStefan Roese }; 194*ff9112dfSStefan Roese 195*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = { 196*ff9112dfSStefan Roese /* Read Leveling */ 197*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 198*ff9112dfSStefan Roese /*0 2 4 15 */ 199*ff9112dfSStefan Roese {0x000016A0, 0xC002040C}, 200*ff9112dfSStefan Roese /*1 2 4 2 */ 201*ff9112dfSStefan Roese {0x000016A0, 0xC0420117}, 202*ff9112dfSStefan Roese /*2 2 4 27 */ 203*ff9112dfSStefan Roese {0x000016A0, 0xC082041B}, 204*ff9112dfSStefan Roese /*3 2 4 0 */ 205*ff9112dfSStefan Roese {0x000016A0, 0xC0C20117}, 206*ff9112dfSStefan Roese /*4 2 4 13 */ 207*ff9112dfSStefan Roese {0x000016A0, 0xC102040A}, 208*ff9112dfSStefan Roese /*5 2 4 5 */ 209*ff9112dfSStefan Roese {0x000016A0, 0xC1420117}, 210*ff9112dfSStefan Roese /*6 2 4 19 */ 211*ff9112dfSStefan Roese {0x000016A0, 0xC1820419}, 212*ff9112dfSStefan Roese /*7 2 4 0 */ 213*ff9112dfSStefan Roese {0x000016A0, 0xC1C20117}, 214*ff9112dfSStefan Roese /*8 2 4 10 */ 215*ff9112dfSStefan Roese {0x000016A0, 0xC2020117}, 216*ff9112dfSStefan Roese 217*ff9112dfSStefan Roese /* Write Leveling */ 218*ff9112dfSStefan Roese /*0 */ 219*ff9112dfSStefan Roese {0x000016A0, 0xC0008113}, 220*ff9112dfSStefan Roese /*1 */ 221*ff9112dfSStefan Roese {0x000016A0, 0xC0404504}, 222*ff9112dfSStefan Roese /*2 */ 223*ff9112dfSStefan Roese {0x000016A0, 0xC0808514}, 224*ff9112dfSStefan Roese /*3 */ 225*ff9112dfSStefan Roese {0x000016A0, 0xC0C09418}, 226*ff9112dfSStefan Roese /*4 */ 227*ff9112dfSStefan Roese {0x000016A0, 0xC1006D0E}, 228*ff9112dfSStefan Roese /*5 */ 229*ff9112dfSStefan Roese {0x000016A0, 0xC1405508}, 230*ff9112dfSStefan Roese /*6 */ 231*ff9112dfSStefan Roese {0x000016A0, 0xC1807D12}, 232*ff9112dfSStefan Roese /*7 */ 233*ff9112dfSStefan Roese {0x000016A0, 0xC1C0b01F}, 234*ff9112dfSStefan Roese /*8 */ 235*ff9112dfSStefan Roese {0x000016A0, 0xC2005D0A}, 236*ff9112dfSStefan Roese 237*ff9112dfSStefan Roese /*center DQS on read cycle */ 238*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 239*ff9112dfSStefan Roese 240*ff9112dfSStefan Roese {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ 241*ff9112dfSStefan Roese {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ 242*ff9112dfSStefan Roese 243*ff9112dfSStefan Roese /*init DRAM */ 244*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 245*ff9112dfSStefan Roese {0x0, 0x0} 246*ff9112dfSStefan Roese }; 247*ff9112dfSStefan Roese 248*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = { 249*ff9112dfSStefan Roese /* Read Leveling */ 250*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 251*ff9112dfSStefan Roese /*0 2 3 1 */ 252*ff9112dfSStefan Roese {0x000016A0, 0xC0020104}, 253*ff9112dfSStefan Roese /*1 2 2 6 */ 254*ff9112dfSStefan Roese {0x000016A0, 0xC0420010}, 255*ff9112dfSStefan Roese /*2 2 3 16 */ 256*ff9112dfSStefan Roese {0x000016A0, 0xC0820112}, 257*ff9112dfSStefan Roese /*3 2 1 26 */ 258*ff9112dfSStefan Roese {0x000016A0, 0xC0C20009}, 259*ff9112dfSStefan Roese /*4 2 2 29 */ 260*ff9112dfSStefan Roese {0x000016A0, 0xC102001F}, 261*ff9112dfSStefan Roese /*5 2 2 13 */ 262*ff9112dfSStefan Roese {0x000016A0, 0xC1420014}, 263*ff9112dfSStefan Roese /*6 2 3 6 */ 264*ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 265*ff9112dfSStefan Roese /*7 2 1 31 */ 266*ff9112dfSStefan Roese {0x000016A0, 0xC1C2000C}, 267*ff9112dfSStefan Roese /*8 2 2 22 */ 268*ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 269*ff9112dfSStefan Roese 270*ff9112dfSStefan Roese /* Write Leveling */ 271*ff9112dfSStefan Roese /*0 */ 272*ff9112dfSStefan Roese {0x000016A0, 0xC0009919}, 273*ff9112dfSStefan Roese /*1 */ 274*ff9112dfSStefan Roese {0x000016A0, 0xC0405508}, 275*ff9112dfSStefan Roese /*2 */ 276*ff9112dfSStefan Roese {0x000016A0, 0xC0809919}, 277*ff9112dfSStefan Roese /*3 */ 278*ff9112dfSStefan Roese {0x000016A0, 0xC0C09C1A}, 279*ff9112dfSStefan Roese /*4 */ 280*ff9112dfSStefan Roese {0x000016A0, 0xC1008113}, 281*ff9112dfSStefan Roese /*5 */ 282*ff9112dfSStefan Roese {0x000016A0, 0xC140650C}, 283*ff9112dfSStefan Roese /*6 */ 284*ff9112dfSStefan Roese {0x000016A0, 0xC1809518}, 285*ff9112dfSStefan Roese /*7 */ 286*ff9112dfSStefan Roese {0x000016A0, 0xC1C04103}, 287*ff9112dfSStefan Roese /*8 */ 288*ff9112dfSStefan Roese {0x000016A0, 0xC2006D0E}, 289*ff9112dfSStefan Roese 290*ff9112dfSStefan Roese /*center DQS on read cycle */ 291*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 292*ff9112dfSStefan Roese 293*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 294*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 295*ff9112dfSStefan Roese /*init DRAM */ 296*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 297*ff9112dfSStefan Roese {0x0, 0x0} 298*ff9112dfSStefan Roese }; 299*ff9112dfSStefan Roese 300*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = { 301*ff9112dfSStefan Roese 302*ff9112dfSStefan Roese /* Read Leveling */ 303*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 304*ff9112dfSStefan Roese /*0 2 3 1 */ 305*ff9112dfSStefan Roese {0x000016A0, 0xC0020103}, 306*ff9112dfSStefan Roese /*1 2 2 6 */ 307*ff9112dfSStefan Roese {0x000016A0, 0xC0420012}, 308*ff9112dfSStefan Roese /*2 2 3 16 */ 309*ff9112dfSStefan Roese {0x000016A0, 0xC0820113}, 310*ff9112dfSStefan Roese /*3 2 1 26 */ 311*ff9112dfSStefan Roese {0x000016A0, 0xC0C20012}, 312*ff9112dfSStefan Roese /*4 2 2 29 */ 313*ff9112dfSStefan Roese {0x000016A0, 0xC1020100}, 314*ff9112dfSStefan Roese /*5 2 2 13 */ 315*ff9112dfSStefan Roese {0x000016A0, 0xC1420016}, 316*ff9112dfSStefan Roese /*6 2 3 6 */ 317*ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 318*ff9112dfSStefan Roese /*7 2 1 31 */ 319*ff9112dfSStefan Roese {0x000016A0, 0xC1C20010}, 320*ff9112dfSStefan Roese /*8 2 2 22 */ 321*ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 322*ff9112dfSStefan Roese 323*ff9112dfSStefan Roese /* Write Leveling */ 324*ff9112dfSStefan Roese /*0 */ 325*ff9112dfSStefan Roese {0x000016A0, 0xC000b11F}, 326*ff9112dfSStefan Roese /*1 */ 327*ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 328*ff9112dfSStefan Roese /*2 */ 329*ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 330*ff9112dfSStefan Roese /*3 */ 331*ff9112dfSStefan Roese {0x000016A0, 0xC0C0a81D}, 332*ff9112dfSStefan Roese /*4 */ 333*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 334*ff9112dfSStefan Roese /*5 */ 335*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 336*ff9112dfSStefan Roese /*6 */ 337*ff9112dfSStefan Roese {0x000016A0, 0xC180ad1e}, 338*ff9112dfSStefan Roese /*7 */ 339*ff9112dfSStefan Roese {0x000016A0, 0xC1C04d06}, 340*ff9112dfSStefan Roese /*8 */ 341*ff9112dfSStefan Roese {0x000016A0, 0xC2008514}, 342*ff9112dfSStefan Roese 343*ff9112dfSStefan Roese /*center DQS on read cycle */ 344*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 345*ff9112dfSStefan Roese 346*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 347*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 348*ff9112dfSStefan Roese 349*ff9112dfSStefan Roese /*init DRAM */ 350*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 351*ff9112dfSStefan Roese {0x0, 0x0} 352*ff9112dfSStefan Roese }; 353*ff9112dfSStefan Roese 354*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = { 355*ff9112dfSStefan Roese 356*ff9112dfSStefan Roese /* Read Leveling */ 357*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 358*ff9112dfSStefan Roese /*0 2 3 1 */ 359*ff9112dfSStefan Roese {0x000016A0, 0xC0020213}, 360*ff9112dfSStefan Roese /*1 2 2 6 */ 361*ff9112dfSStefan Roese {0x000016A0, 0xC0420108}, 362*ff9112dfSStefan Roese /*2 2 3 16 */ 363*ff9112dfSStefan Roese {0x000016A0, 0xC0820210}, 364*ff9112dfSStefan Roese /*3 2 1 26 */ 365*ff9112dfSStefan Roese {0x000016A0, 0xC0C20108}, 366*ff9112dfSStefan Roese /*4 2 2 29 */ 367*ff9112dfSStefan Roese {0x000016A0, 0xC102011A}, 368*ff9112dfSStefan Roese /*5 2 2 13 */ 369*ff9112dfSStefan Roese {0x000016A0, 0xC1420300}, 370*ff9112dfSStefan Roese /*6 2 3 6 */ 371*ff9112dfSStefan Roese {0x000016A0, 0xC1820204}, 372*ff9112dfSStefan Roese /*7 2 1 31 */ 373*ff9112dfSStefan Roese {0x000016A0, 0xC1C20106}, 374*ff9112dfSStefan Roese /*8 2 2 22 */ 375*ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 376*ff9112dfSStefan Roese 377*ff9112dfSStefan Roese /* Write Leveling */ 378*ff9112dfSStefan Roese /*0 */ 379*ff9112dfSStefan Roese {0x000016A0, 0xC000620B}, 380*ff9112dfSStefan Roese /*1 */ 381*ff9112dfSStefan Roese {0x000016A0, 0xC0408D16}, 382*ff9112dfSStefan Roese /*2 */ 383*ff9112dfSStefan Roese {0x000016A0, 0xC0806A0D}, 384*ff9112dfSStefan Roese /*3 */ 385*ff9112dfSStefan Roese {0x000016A0, 0xC0C03D02}, 386*ff9112dfSStefan Roese /*4 */ 387*ff9112dfSStefan Roese {0x000016A0, 0xC1004a05}, 388*ff9112dfSStefan Roese /*5 */ 389*ff9112dfSStefan Roese {0x000016A0, 0xC140A11B}, 390*ff9112dfSStefan Roese /*6 */ 391*ff9112dfSStefan Roese {0x000016A0, 0xC1805E0A}, 392*ff9112dfSStefan Roese /*7 */ 393*ff9112dfSStefan Roese {0x000016A0, 0xC1C06D0E}, 394*ff9112dfSStefan Roese /*8 */ 395*ff9112dfSStefan Roese {0x000016A0, 0xC200AD1E}, 396*ff9112dfSStefan Roese 397*ff9112dfSStefan Roese /*center DQS on read cycle */ 398*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 399*ff9112dfSStefan Roese 400*ff9112dfSStefan Roese {0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */ 401*ff9112dfSStefan Roese {0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */ 402*ff9112dfSStefan Roese 403*ff9112dfSStefan Roese /*init DRAM */ 404*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 405*ff9112dfSStefan Roese {0x0, 0x0} 406*ff9112dfSStefan Roese }; 407*ff9112dfSStefan Roese 408*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = { 409*ff9112dfSStefan Roese /* Read Leveling */ 410*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 411*ff9112dfSStefan Roese /*0 */ 412*ff9112dfSStefan Roese {0x000016A0, 0xC002010E}, 413*ff9112dfSStefan Roese /*1 */ 414*ff9112dfSStefan Roese {0x000016A0, 0xC042001E}, 415*ff9112dfSStefan Roese /*2 */ 416*ff9112dfSStefan Roese {0x000016A0, 0xC0820118}, 417*ff9112dfSStefan Roese /*3 */ 418*ff9112dfSStefan Roese {0x000016A0, 0xC0C2001E}, 419*ff9112dfSStefan Roese /*4 */ 420*ff9112dfSStefan Roese {0x000016A0, 0xC102010C}, 421*ff9112dfSStefan Roese /*5 */ 422*ff9112dfSStefan Roese {0x000016A0, 0xC1420102}, 423*ff9112dfSStefan Roese /*6 */ 424*ff9112dfSStefan Roese {0x000016A0, 0xC1820111}, 425*ff9112dfSStefan Roese /*7 */ 426*ff9112dfSStefan Roese {0x000016A0, 0xC1C2001C}, 427*ff9112dfSStefan Roese /*8 */ 428*ff9112dfSStefan Roese {0x000016A0, 0xC2020109}, 429*ff9112dfSStefan Roese 430*ff9112dfSStefan Roese /* Write Leveling */ 431*ff9112dfSStefan Roese /*0 */ 432*ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 433*ff9112dfSStefan Roese /*1 */ 434*ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 435*ff9112dfSStefan Roese /*2 */ 436*ff9112dfSStefan Roese {0x000016A0, 0xC0805207}, 437*ff9112dfSStefan Roese /*3 */ 438*ff9112dfSStefan Roese {0x000016A0, 0xC0C0A81D}, 439*ff9112dfSStefan Roese /*4 */ 440*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 441*ff9112dfSStefan Roese /*5 */ 442*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 443*ff9112dfSStefan Roese /*6 */ 444*ff9112dfSStefan Roese {0x000016A0, 0xC1803E02}, 445*ff9112dfSStefan Roese /*7 */ 446*ff9112dfSStefan Roese {0x000016A0, 0xC1C05107}, 447*ff9112dfSStefan Roese /*8 */ 448*ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 449*ff9112dfSStefan Roese 450*ff9112dfSStefan Roese /*center DQS on read cycle */ 451*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 452*ff9112dfSStefan Roese 453*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 454*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 455*ff9112dfSStefan Roese 456*ff9112dfSStefan Roese /*init DRAM */ 457*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 458*ff9112dfSStefan Roese {0x0, 0x0} 459*ff9112dfSStefan Roese }; 460*ff9112dfSStefan Roese 461*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = { 462*ff9112dfSStefan Roese /* Read Leveling */ 463*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 464*ff9112dfSStefan Roese /*0 */ 465*ff9112dfSStefan Roese {0x000016A0, 0xC0020106}, 466*ff9112dfSStefan Roese /*1 */ 467*ff9112dfSStefan Roese {0x000016A0, 0xC0420016}, 468*ff9112dfSStefan Roese /*2 */ 469*ff9112dfSStefan Roese {0x000016A0, 0xC0820117}, 470*ff9112dfSStefan Roese /*3 */ 471*ff9112dfSStefan Roese {0x000016A0, 0xC0C2000F}, 472*ff9112dfSStefan Roese /*4 */ 473*ff9112dfSStefan Roese {0x000016A0, 0xC1020105}, 474*ff9112dfSStefan Roese /*5 */ 475*ff9112dfSStefan Roese {0x000016A0, 0xC142001B}, 476*ff9112dfSStefan Roese /*6 */ 477*ff9112dfSStefan Roese {0x000016A0, 0xC182010C}, 478*ff9112dfSStefan Roese /*7 */ 479*ff9112dfSStefan Roese {0x000016A0, 0xC1C20011}, 480*ff9112dfSStefan Roese /*8 */ 481*ff9112dfSStefan Roese {0x000016A0, 0xC2020101}, 482*ff9112dfSStefan Roese 483*ff9112dfSStefan Roese /* Write Leveling */ 484*ff9112dfSStefan Roese /*0 */ 485*ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 486*ff9112dfSStefan Roese /*1 */ 487*ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 488*ff9112dfSStefan Roese /*2 */ 489*ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 490*ff9112dfSStefan Roese /*3 */ 491*ff9112dfSStefan Roese {0x000016A0, 0xC0C04504}, 492*ff9112dfSStefan Roese /*4 */ 493*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 494*ff9112dfSStefan Roese /*5 */ 495*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 496*ff9112dfSStefan Roese /*6 */ 497*ff9112dfSStefan Roese {0x000016A0, 0xC1803600}, 498*ff9112dfSStefan Roese /*7 */ 499*ff9112dfSStefan Roese {0x000016A0, 0xC1C0610B}, 500*ff9112dfSStefan Roese /*8 */ 501*ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 502*ff9112dfSStefan Roese 503*ff9112dfSStefan Roese /*center DQS on read cycle */ 504*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 505*ff9112dfSStefan Roese 506*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 507*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 508*ff9112dfSStefan Roese 509*ff9112dfSStefan Roese /*init DRAM */ 510*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 511*ff9112dfSStefan Roese {0x0, 0x0} 512*ff9112dfSStefan Roese }; 513*ff9112dfSStefan Roese 514*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = { 515*ff9112dfSStefan Roese /* Read Leveling */ 516*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 517*ff9112dfSStefan Roese /*0 */ 518*ff9112dfSStefan Roese {0x000016A0, 0xC002010C}, 519*ff9112dfSStefan Roese /*1 */ 520*ff9112dfSStefan Roese {0x000016A0, 0xC042001B}, 521*ff9112dfSStefan Roese /*2 */ 522*ff9112dfSStefan Roese {0x000016A0, 0xC082011D}, 523*ff9112dfSStefan Roese /*3 */ 524*ff9112dfSStefan Roese {0x000016A0, 0xC0C20015}, 525*ff9112dfSStefan Roese /*4 */ 526*ff9112dfSStefan Roese {0x000016A0, 0xC102010B}, 527*ff9112dfSStefan Roese /*5 */ 528*ff9112dfSStefan Roese {0x000016A0, 0xC1420101}, 529*ff9112dfSStefan Roese /*6 */ 530*ff9112dfSStefan Roese {0x000016A0, 0xC1820113}, 531*ff9112dfSStefan Roese /*7 */ 532*ff9112dfSStefan Roese {0x000016A0, 0xC1C20017}, 533*ff9112dfSStefan Roese /*8 */ 534*ff9112dfSStefan Roese {0x000016A0, 0xC2020107}, 535*ff9112dfSStefan Roese 536*ff9112dfSStefan Roese /* Write Leveling */ 537*ff9112dfSStefan Roese /*0 */ 538*ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 539*ff9112dfSStefan Roese /*1 */ 540*ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 541*ff9112dfSStefan Roese /*2 */ 542*ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 543*ff9112dfSStefan Roese /*3 */ 544*ff9112dfSStefan Roese {0x000016A0, 0xC0C04504}, 545*ff9112dfSStefan Roese /*4 */ 546*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 547*ff9112dfSStefan Roese /*5 */ 548*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 549*ff9112dfSStefan Roese /*6 */ 550*ff9112dfSStefan Roese {0x000016A0, 0xC180B11F}, 551*ff9112dfSStefan Roese /*7 */ 552*ff9112dfSStefan Roese {0x000016A0, 0xC1C0610B}, 553*ff9112dfSStefan Roese /*8 */ 554*ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 555*ff9112dfSStefan Roese 556*ff9112dfSStefan Roese /*center DQS on read cycle */ 557*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 558*ff9112dfSStefan Roese 559*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 560*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 561*ff9112dfSStefan Roese 562*ff9112dfSStefan Roese /*init DRAM */ 563*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 564*ff9112dfSStefan Roese {0x0, 0x0} 565*ff9112dfSStefan Roese }; 566*ff9112dfSStefan Roese 567*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = { 568*ff9112dfSStefan Roese /* Read Leveling */ 569*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 570*ff9112dfSStefan Roese /* CS 0 */ 571*ff9112dfSStefan Roese /*0 2 3 1 */ 572*ff9112dfSStefan Roese {0x000016A0, 0xC0020103}, 573*ff9112dfSStefan Roese /*1 2 2 6 */ 574*ff9112dfSStefan Roese {0x000016A0, 0xC0420012}, 575*ff9112dfSStefan Roese /*2 2 3 16 */ 576*ff9112dfSStefan Roese {0x000016A0, 0xC0820113}, 577*ff9112dfSStefan Roese /*3 2 1 26 */ 578*ff9112dfSStefan Roese {0x000016A0, 0xC0C20012}, 579*ff9112dfSStefan Roese /*4 2 2 29 */ 580*ff9112dfSStefan Roese {0x000016A0, 0xC1020100}, 581*ff9112dfSStefan Roese /*5 2 2 13 */ 582*ff9112dfSStefan Roese {0x000016A0, 0xC1420016}, 583*ff9112dfSStefan Roese /*6 2 3 6 */ 584*ff9112dfSStefan Roese {0x000016A0, 0xC1820109}, 585*ff9112dfSStefan Roese /*7 2 1 31 */ 586*ff9112dfSStefan Roese {0x000016A0, 0xC1C20010}, 587*ff9112dfSStefan Roese /*8 2 2 22 */ 588*ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 589*ff9112dfSStefan Roese 590*ff9112dfSStefan Roese /* Write Leveling */ 591*ff9112dfSStefan Roese /*0 */ 592*ff9112dfSStefan Roese {0x000016A0, 0xC000b11F}, 593*ff9112dfSStefan Roese /*1 */ 594*ff9112dfSStefan Roese {0x000016A0, 0xC040690D}, 595*ff9112dfSStefan Roese /*2 */ 596*ff9112dfSStefan Roese {0x000016A0, 0xC0803600}, 597*ff9112dfSStefan Roese /*3 */ 598*ff9112dfSStefan Roese {0x000016A0, 0xC0C0a81D}, 599*ff9112dfSStefan Roese /*4 */ 600*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 601*ff9112dfSStefan Roese /*5 */ 602*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 603*ff9112dfSStefan Roese /*6 */ 604*ff9112dfSStefan Roese {0x000016A0, 0xC180ad1e}, 605*ff9112dfSStefan Roese /*7 */ 606*ff9112dfSStefan Roese {0x000016A0, 0xC1C04d06}, 607*ff9112dfSStefan Roese /*8 */ 608*ff9112dfSStefan Roese {0x000016A0, 0xC2008514}, 609*ff9112dfSStefan Roese 610*ff9112dfSStefan Roese /*center DQS on read cycle */ 611*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 612*ff9112dfSStefan Roese 613*ff9112dfSStefan Roese /* CS 1 */ 614*ff9112dfSStefan Roese 615*ff9112dfSStefan Roese {0x000016A0, 0xC0060103}, 616*ff9112dfSStefan Roese /*1 2 2 6 */ 617*ff9112dfSStefan Roese {0x000016A0, 0xC0460012}, 618*ff9112dfSStefan Roese /*2 2 3 16 */ 619*ff9112dfSStefan Roese {0x000016A0, 0xC0860113}, 620*ff9112dfSStefan Roese /*3 2 1 26 */ 621*ff9112dfSStefan Roese {0x000016A0, 0xC0C60012}, 622*ff9112dfSStefan Roese /*4 2 2 29 */ 623*ff9112dfSStefan Roese {0x000016A0, 0xC1060100}, 624*ff9112dfSStefan Roese /*5 2 2 13 */ 625*ff9112dfSStefan Roese {0x000016A0, 0xC1460016}, 626*ff9112dfSStefan Roese /*6 2 3 6 */ 627*ff9112dfSStefan Roese {0x000016A0, 0xC1860109}, 628*ff9112dfSStefan Roese /*7 2 1 31 */ 629*ff9112dfSStefan Roese {0x000016A0, 0xC1C60010}, 630*ff9112dfSStefan Roese /*8 2 2 22 */ 631*ff9112dfSStefan Roese {0x000016A0, 0xC2060112}, 632*ff9112dfSStefan Roese 633*ff9112dfSStefan Roese /* Write Leveling */ 634*ff9112dfSStefan Roese /*0 */ 635*ff9112dfSStefan Roese {0x000016A0, 0xC004b11F}, 636*ff9112dfSStefan Roese /*1 */ 637*ff9112dfSStefan Roese {0x000016A0, 0xC044690D}, 638*ff9112dfSStefan Roese /*2 */ 639*ff9112dfSStefan Roese {0x000016A0, 0xC0843600}, 640*ff9112dfSStefan Roese /*3 */ 641*ff9112dfSStefan Roese {0x000016A0, 0xC0C4a81D}, 642*ff9112dfSStefan Roese /*4 */ 643*ff9112dfSStefan Roese {0x000016A0, 0xC1049919}, 644*ff9112dfSStefan Roese /*5 */ 645*ff9112dfSStefan Roese {0x000016A0, 0xC1447911}, 646*ff9112dfSStefan Roese /*6 */ 647*ff9112dfSStefan Roese {0x000016A0, 0xC184ad1e}, 648*ff9112dfSStefan Roese /*7 */ 649*ff9112dfSStefan Roese {0x000016A0, 0xC1C44d06}, 650*ff9112dfSStefan Roese /*8 */ 651*ff9112dfSStefan Roese {0x000016A0, 0xC2048514}, 652*ff9112dfSStefan Roese 653*ff9112dfSStefan Roese /*center DQS on read cycle */ 654*ff9112dfSStefan Roese {0x000016A0, 0xC807000F}, 655*ff9112dfSStefan Roese 656*ff9112dfSStefan Roese /* Both CS */ 657*ff9112dfSStefan Roese 658*ff9112dfSStefan Roese {0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */ 659*ff9112dfSStefan Roese {0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */ 660*ff9112dfSStefan Roese 661*ff9112dfSStefan Roese /*init DRAM */ 662*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 663*ff9112dfSStefan Roese {0x0, 0x0} 664*ff9112dfSStefan Roese }; 665*ff9112dfSStefan Roese 666*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = { 667*ff9112dfSStefan Roese /* Read Leveling */ 668*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 669*ff9112dfSStefan Roese /*0 */ 670*ff9112dfSStefan Roese {0x000016A0, 0xC0020118}, 671*ff9112dfSStefan Roese /*1 */ 672*ff9112dfSStefan Roese {0x000016A0, 0xC0420108}, 673*ff9112dfSStefan Roese /*2 */ 674*ff9112dfSStefan Roese {0x000016A0, 0xC0820202}, 675*ff9112dfSStefan Roese /*3 */ 676*ff9112dfSStefan Roese {0x000016A0, 0xC0C20108}, 677*ff9112dfSStefan Roese /*4 */ 678*ff9112dfSStefan Roese {0x000016A0, 0xC1020117}, 679*ff9112dfSStefan Roese /*5 */ 680*ff9112dfSStefan Roese {0x000016A0, 0xC142010C}, 681*ff9112dfSStefan Roese /*6 */ 682*ff9112dfSStefan Roese {0x000016A0, 0xC182011B}, 683*ff9112dfSStefan Roese /*7 */ 684*ff9112dfSStefan Roese {0x000016A0, 0xC1C20107}, 685*ff9112dfSStefan Roese /*8 */ 686*ff9112dfSStefan Roese {0x000016A0, 0xC2020113}, 687*ff9112dfSStefan Roese 688*ff9112dfSStefan Roese /* Write Leveling */ 689*ff9112dfSStefan Roese /*0 */ 690*ff9112dfSStefan Roese {0x000016A0, 0xC0003600}, 691*ff9112dfSStefan Roese /*1 */ 692*ff9112dfSStefan Roese {0x000016A0, 0xC0406D0E}, 693*ff9112dfSStefan Roese /*2 */ 694*ff9112dfSStefan Roese {0x000016A0, 0xC0805207}, 695*ff9112dfSStefan Roese /*3 */ 696*ff9112dfSStefan Roese {0x000016A0, 0xC0C0A81D}, 697*ff9112dfSStefan Roese /*4 */ 698*ff9112dfSStefan Roese {0x000016A0, 0xC1009919}, 699*ff9112dfSStefan Roese /*5 */ 700*ff9112dfSStefan Roese {0x000016A0, 0xC1407911}, 701*ff9112dfSStefan Roese /*6 */ 702*ff9112dfSStefan Roese {0x000016A0, 0xC1803E02}, 703*ff9112dfSStefan Roese /*7 */ 704*ff9112dfSStefan Roese {0x000016A0, 0xC1C04D06}, 705*ff9112dfSStefan Roese /*8 */ 706*ff9112dfSStefan Roese {0x000016A0, 0xC2008113}, 707*ff9112dfSStefan Roese 708*ff9112dfSStefan Roese /*center DQS on read cycle */ 709*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 710*ff9112dfSStefan Roese 711*ff9112dfSStefan Roese {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ 712*ff9112dfSStefan Roese {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ 713*ff9112dfSStefan Roese 714*ff9112dfSStefan Roese /*init DRAM */ 715*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 716*ff9112dfSStefan Roese {0x0, 0x0} 717*ff9112dfSStefan Roese }; 718*ff9112dfSStefan Roese 719*ff9112dfSStefan Roese MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = { 720*ff9112dfSStefan Roese /* Read Leveling */ 721*ff9112dfSStefan Roese /*PUP RdSampleDly (+CL) Phase RL ADLL value */ 722*ff9112dfSStefan Roese /*0 */ 723*ff9112dfSStefan Roese {0x000016A0, 0xC0020404}, 724*ff9112dfSStefan Roese /* 1 2 2 6 */ 725*ff9112dfSStefan Roese {0x000016A0, 0xC042031E}, 726*ff9112dfSStefan Roese /* 2 2 3 16 */ 727*ff9112dfSStefan Roese {0x000016A0, 0xC0820411}, 728*ff9112dfSStefan Roese /* 3 2 1 26 */ 729*ff9112dfSStefan Roese {0x000016A0, 0xC0C20400}, 730*ff9112dfSStefan Roese /* 4 2 2 29 */ 731*ff9112dfSStefan Roese {0x000016A0, 0xC1020404}, 732*ff9112dfSStefan Roese /* 5 2 2 13 */ 733*ff9112dfSStefan Roese {0x000016A0, 0xC142031D}, 734*ff9112dfSStefan Roese /* 6 2 3 6 */ 735*ff9112dfSStefan Roese {0x000016A0, 0xC182040C}, 736*ff9112dfSStefan Roese /* 7 2 1 31 */ 737*ff9112dfSStefan Roese {0x000016A0, 0xC1C2031B}, 738*ff9112dfSStefan Roese /* 8 2 2 22 */ 739*ff9112dfSStefan Roese {0x000016A0, 0xC2020112}, 740*ff9112dfSStefan Roese 741*ff9112dfSStefan Roese /* Write Leveling */ 742*ff9112dfSStefan Roese /* 0 */ 743*ff9112dfSStefan Roese {0x000016A0, 0xC0004905}, 744*ff9112dfSStefan Roese /* 1 */ 745*ff9112dfSStefan Roese {0x000016A0, 0xC040A81D}, 746*ff9112dfSStefan Roese /* 2 */ 747*ff9112dfSStefan Roese {0x000016A0, 0xC0804504}, 748*ff9112dfSStefan Roese /* 3 */ 749*ff9112dfSStefan Roese {0x000016A0, 0xC0C08013}, 750*ff9112dfSStefan Roese /* 4 */ 751*ff9112dfSStefan Roese {0x000016A0, 0xC1004504}, 752*ff9112dfSStefan Roese /* 5 */ 753*ff9112dfSStefan Roese {0x000016A0, 0xC140A81D}, 754*ff9112dfSStefan Roese /* 6 */ 755*ff9112dfSStefan Roese {0x000016A0, 0xC1805909}, 756*ff9112dfSStefan Roese /* 7 */ 757*ff9112dfSStefan Roese {0x000016A0, 0xC1C09418}, 758*ff9112dfSStefan Roese /* 8 */ 759*ff9112dfSStefan Roese {0x000016A0, 0xC2006D0E}, 760*ff9112dfSStefan Roese 761*ff9112dfSStefan Roese /*center DQS on read cycle */ 762*ff9112dfSStefan Roese {0x000016A0, 0xC803000F}, 763*ff9112dfSStefan Roese {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ 764*ff9112dfSStefan Roese {0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */ 765*ff9112dfSStefan Roese /* init DRAM */ 766*ff9112dfSStefan Roese {0x00001480, 0x00000001}, 767*ff9112dfSStefan Roese {0x0, 0x0} 768*ff9112dfSStefan Roese }; 769*ff9112dfSStefan Roese 770*ff9112dfSStefan Roese #endif /* __AXP_TRAINING_STATIC_H */ 771