1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2ff9112dfSStefan Roese /* 3ff9112dfSStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4ff9112dfSStefan Roese */ 5ff9112dfSStefan Roese 6ff9112dfSStefan Roese #ifndef __DDR3_AXP_CONFIG_H 7ff9112dfSStefan Roese #define __DDR3_AXP_CONFIG_H 8ff9112dfSStefan Roese 9ff9112dfSStefan Roese /* 10ff9112dfSStefan Roese * DDR3_LOG_LEVEL Information 11ff9112dfSStefan Roese * 12ff9112dfSStefan Roese * Level 0: Provides an error code in a case of failure, RL, WL errors 13ff9112dfSStefan Roese * and other algorithm failure 14ff9112dfSStefan Roese * Level 1: Provides the D-Unit setup (SPD/Static configuration) 15ff9112dfSStefan Roese * Level 2: Provides the windows margin as a results of DQS centeralization 16ff9112dfSStefan Roese * Level 3: Provides the windows margin of each DQ as a results of DQS 17ff9112dfSStefan Roese * centeralization 18ff9112dfSStefan Roese */ 19ff9112dfSStefan Roese #ifdef CONFIG_DDR_LOG_LEVEL 20ff9112dfSStefan Roese #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL 21ff9112dfSStefan Roese #else 22ff9112dfSStefan Roese #define DDR3_LOG_LEVEL 0 23ff9112dfSStefan Roese #endif 24ff9112dfSStefan Roese 25ff9112dfSStefan Roese #define DDR3_PBS 1 26ff9112dfSStefan Roese 27ff9112dfSStefan Roese /* This flag allows the execution of SW WL/RL upon HW failure */ 28ff9112dfSStefan Roese #define DDR3_RUN_SW_WHEN_HW_FAIL 1 29ff9112dfSStefan Roese 30ff9112dfSStefan Roese /* 31ff9112dfSStefan Roese * General Configurations 32ff9112dfSStefan Roese * 33ff9112dfSStefan Roese * The following parameters are required for proper setup: 34ff9112dfSStefan Roese * 35ff9112dfSStefan Roese * DDR_TARGET_FABRIC - Set desired fabric configuration 36ff9112dfSStefan Roese * (for sample@Reset fabfreq parameter) 37ff9112dfSStefan Roese * DRAM_ECC - Set ECC support 1/0 38ff9112dfSStefan Roese * BUS_WIDTH - 64/32 bit 39ff9112dfSStefan Roese * CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values 40ff9112dfSStefan Roese * DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board 41ff9112dfSStefan Roese * MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers 42ff9112dfSStefan Roese * values are taken statically) 43ff9112dfSStefan Roese * DDR3_TRAINING_DEBUG - Debug prints of internal code 44ff9112dfSStefan Roese */ 45ff9112dfSStefan Roese #define DDR_TARGET_FABRIC 5 46698ffab2SStefan Roese /* Only enable ECC if the board selects it */ 47698ffab2SStefan Roese #ifdef CONFIG_BOARD_ECC_SUPPORT 48a3ed9789SStefan Roese #define DRAM_ECC 1 49698ffab2SStefan Roese #else 50698ffab2SStefan Roese #define DRAM_ECC 0 51698ffab2SStefan Roese #endif 52ff9112dfSStefan Roese 534444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT 54ff9112dfSStefan Roese #define BUS_WIDTH 32 55ff9112dfSStefan Roese #else 56ff9112dfSStefan Roese #define BUS_WIDTH 64 57ff9112dfSStefan Roese #endif 58ff9112dfSStefan Roese 59ff9112dfSStefan Roese #undef DQS_CLK_ALIGNED 60ff9112dfSStefan Roese #undef MIXED_DIMM_STATIC 61ff9112dfSStefan Roese #define DDR3_TRAINING_DEBUG 0 62ff9112dfSStefan Roese #define REG_DIMM_SKIP_WL 0 63ff9112dfSStefan Roese 64ff9112dfSStefan Roese /* Marvell boards specific configurations */ 65ff9112dfSStefan Roese #if defined(DB_78X60_PCAC) 66ff9112dfSStefan Roese #undef CONFIG_SPD_EEPROM 67ff9112dfSStefan Roese #define STATIC_TRAINING 68ff9112dfSStefan Roese #endif 69ff9112dfSStefan Roese 70ff9112dfSStefan Roese #if defined(DB_78X60_AMC) 71ff9112dfSStefan Roese #undef CONFIG_SPD_EEPROM 72ff9112dfSStefan Roese #undef DRAM_ECC 73ff9112dfSStefan Roese #define DRAM_ECC 1 74ff9112dfSStefan Roese #endif 75ff9112dfSStefan Roese 76ff9112dfSStefan Roese #ifdef CONFIG_SPD_EEPROM 77ff9112dfSStefan Roese /* 78ff9112dfSStefan Roese * DIMM support parameters: 79ff9112dfSStefan Roese * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T 80ff9112dfSStefan Roese * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs 81ff9112dfSStefan Roese * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...) 82ff9112dfSStefan Roese */ 83ff9112dfSStefan Roese #define DRAM_2T 0x0 84ff9112dfSStefan Roese #define DIMM_CS_BITMAP 0xF 85ff9112dfSStefan Roese #define DUNIT_SPD 86ff9112dfSStefan Roese #endif 87ff9112dfSStefan Roese 88ff9112dfSStefan Roese #ifdef DRAM_ECC 89ff9112dfSStefan Roese /* 90ff9112dfSStefan Roese * ECC support parameters: 91ff9112dfSStefan Roese * 92ff9112dfSStefan Roese * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need 93ff9112dfSStefan Roese * to configure the scrubbing area 94ff9112dfSStefan Roese */ 95ff9112dfSStefan Roese #define TRAINING_SIZE 0x20000 96ff9112dfSStefan Roese #define U_BOOT_START_ADDR 0 97ff9112dfSStefan Roese #define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */ 98ff9112dfSStefan Roese #endif 99ff9112dfSStefan Roese 100ff9112dfSStefan Roese /* 101ff9112dfSStefan Roese * Registered DIMM Support - In case registered DIMM is attached, 102ff9112dfSStefan Roese * please supply the following values: 103ff9112dfSStefan Roese * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock 104ff9112dfSStefan Roese * Driver with Parity and Quad Chip 105ff9112dfSStefan Roese * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications") 106ff9112dfSStefan Roese * RC0: Global Features Control Word 107ff9112dfSStefan Roese * RC1: Clock Driver Enable Control Word 108ff9112dfSStefan Roese * RC2: Timing Control Word 109ff9112dfSStefan Roese * RC3-RC5 - taken from SPD 110ff9112dfSStefan Roese * RC8: Additional IBT Setting Control Word 111ff9112dfSStefan Roese * RC9: Power Saving Settings Control Word 112ff9112dfSStefan Roese * RC10: Encoding for RDIMM Operating Speed 113ff9112dfSStefan Roese * RC11: Operating Voltage VDD and VREFCA Control Word 114ff9112dfSStefan Roese */ 115ff9112dfSStefan Roese #define RDIMM_RC0 0 116ff9112dfSStefan Roese #define RDIMM_RC1 0 117ff9112dfSStefan Roese #define RDIMM_RC2 0 118ff9112dfSStefan Roese #define RDIMM_RC8 0 119ff9112dfSStefan Roese #define RDIMM_RC9 0 120ff9112dfSStefan Roese #define RDIMM_RC10 0x2 121ff9112dfSStefan Roese #define RDIMM_RC11 0x0 122ff9112dfSStefan Roese 123ff9112dfSStefan Roese #if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM) 124ff9112dfSStefan Roese #define DUNIT_STATIC 125ff9112dfSStefan Roese #endif 126ff9112dfSStefan Roese 127ff9112dfSStefan Roese #if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM) 128ff9112dfSStefan Roese /* 129ff9112dfSStefan Roese * This flag allows the user to change the dram refresh cycle in ps, 130ff9112dfSStefan Roese * only in case of SPD or MIX DIMM topology 131ff9112dfSStefan Roese */ 132ff9112dfSStefan Roese #define TREFI_USER_EN 133ff9112dfSStefan Roese 134ff9112dfSStefan Roese #ifdef TREFI_USER_EN 135ff9112dfSStefan Roese #define TREFI_USER 3900000 136ff9112dfSStefan Roese #endif 137ff9112dfSStefan Roese #endif 138ff9112dfSStefan Roese 139ff9112dfSStefan Roese #ifdef CONFIG_SPD_EEPROM 140ff9112dfSStefan Roese /* 141ff9112dfSStefan Roese * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards. 142ff9112dfSStefan Roese * Enables I2C auto detection different options 143ff9112dfSStefan Roese */ 144ff9112dfSStefan Roese #if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \ 145ff9112dfSStefan Roese defined(CONFIG_DB_784MP_GP) 146ff9112dfSStefan Roese #define AUTO_DETECTION_SUPPORT 147ff9112dfSStefan Roese #endif 148ff9112dfSStefan Roese #endif 149ff9112dfSStefan Roese 150ff9112dfSStefan Roese #endif /* __DDR3_AXP_CONFIG_H */ 151