1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __DDR3_AXP_H 8 #define __DDR3_AXP_H 9 10 #define MV_78XX0_Z1_REV 0x0 11 #define MV_78XX0_A0_REV 0x1 12 #define MV_78XX0_B0_REV 0x2 13 14 #define SAR_DDR3_FREQ_MASK 0xFE00000 15 #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24)) 16 17 #define MAX_CS 4 18 19 #define MIN_DIMM_ADDR 0x50 20 #define FAR_END_DIMM_ADDR 0x50 21 #define MAX_DIMM_ADDR 0x60 22 23 #ifndef CONFIG_DDR_FIXED_SIZE 24 #define SDRAM_CS_SIZE 0xFFFFFFF 25 #else 26 #define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) 27 #endif 28 #define SDRAM_CS_BASE 0x0 29 #define SDRAM_DIMM_SIZE 0x80000000 30 31 #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) 32 #define CPU_MRVL_ID_OFFSET 0x10 33 #define SAR1_CPU_CORE_MASK 0x00000018 34 #define SAR1_CPU_CORE_OFFSET 3 35 36 #define ECC_SUPPORT 37 #define NEW_FABRIC_TWSI_ADDR 0x4E 38 #ifdef CONFIG_DB_784MP_GP 39 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E 40 #else 41 #define BUS_WIDTH_ECC_TWSI_ADDR 0x4F 42 #endif 43 #define MV_MAX_DDR3_STATIC_SIZE 50 44 #define MV_DDR3_MODES_NUMBER 30 45 46 #define RESUME_RL_PATTERNS_ADDR (0xFE0000) 47 #define RESUME_RL_PATTERNS_SIZE (0x100) 48 #define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE) 49 #define RESUME_TRAINING_VALUES_MAX (0xCD0) 50 #define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000) 51 #define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000) 52 #define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4) 53 #define SUSPEND_MAGIC_WORD (0xDEADB002) 54 #define REGISTER_LIST_END (0xFFFFFFFF) 55 56 /* 57 * Registers offset 58 */ 59 60 #define REG_SAMPLE_RESET_LOW_ADDR 0x18230 61 #define REG_SAMPLE_RESET_HIGH_ADDR 0x18234 62 #define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21 63 #define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000 64 #define REG_SAMPLE_RESET_FAB_OFFS 24 65 #define REG_SAMPLE_RESET_FAB_MASK 0xF000000 66 #define REG_SAMPLE_RESET_TCLK_OFFS 28 67 #define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31 68 #define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20 69 70 /* MISC */ 71 /* 72 * In mainline U-Boot we're re-configuring the mvebu base address 73 * register to 0xf1000000. So need to use this value for the DDR 74 * training code as well. 75 */ 76 #define INTER_REGS_BASE SOC_REGS_PHY_BASE 77 78 /* DDR */ 79 #define REG_SDRAM_CONFIG_ADDR 0x1400 80 #define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF 81 #define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF 82 #define REG_SDRAM_CONFIG_WIDTH_OFFS 15 83 #define REG_SDRAM_CONFIG_REGDIMM_OFFS 17 84 #define REG_SDRAM_CONFIG_ECC_OFFS 18 85 #define REG_SDRAM_CONFIG_IERR_OFFS 19 86 #define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28 87 #define REG_SDRAM_CONFIG_RSTRD_OFFS 30 88 89 #define REG_DUNIT_CTRL_LOW_ADDR 0x1404 90 #define REG_DUNIT_CTRL_LOW_2T_OFFS 3 91 #define REG_DUNIT_CTRL_LOW_2T_MASK 0x3 92 #define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14 93 94 #define REG_SDRAM_TIMING_LOW_ADDR 0x1408 95 96 #define REG_SDRAM_TIMING_HIGH_ADDR 0x140C 97 #define REG_SDRAM_TIMING_H_R2R_OFFS 7 98 #define REG_SDRAM_TIMING_H_R2R_MASK 0x3 99 #define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9 100 #define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3 101 #define REG_SDRAM_TIMING_H_W2W_OFFS 11 102 #define REG_SDRAM_TIMING_H_W2W_MASK 0x1F 103 #define REG_SDRAM_TIMING_H_R2R_H_OFFS 19 104 #define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7 105 #define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22 106 #define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7 107 108 #define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410 109 #define REG_SDRAM_ADDRESS_SIZE_OFFS 2 110 #define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18 111 #define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4 112 113 #define REG_SDRAM_OPEN_PAGES_ADDR 0x1414 114 #define REG_SDRAM_OPERATION_CS_OFFS 8 115 116 #define REG_SDRAM_OPERATION_ADDR 0x1418 117 #define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24 118 #define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20 119 #define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF 120 #define REG_SDRAM_OPERATION_CWA_RC_OFFS 16 121 #define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF 122 #define REG_SDRAM_OPERATION_CMD_MR0 0xF03 123 #define REG_SDRAM_OPERATION_CMD_MR1 0xF04 124 #define REG_SDRAM_OPERATION_CMD_MR2 0xF08 125 #define REG_SDRAM_OPERATION_CMD_MR3 0xF09 126 #define REG_SDRAM_OPERATION_CMD_RFRS 0xF02 127 #define REG_SDRAM_OPERATION_CMD_CWA 0xF0E 128 #define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF 129 #define REG_SDRAM_OPERATION_CMD_MASK 0xF 130 #define REG_SDRAM_OPERATION_CS_OFFS 8 131 132 #define REG_OUDDR3_TIMING_ADDR 0x142C 133 134 #define REG_SDRAM_MODE_ADDR 0x141C 135 136 #define REG_SDRAM_EXT_MODE_ADDR 0x1420 137 138 #define REG_DDR_CONT_HIGH_ADDR 0x1424 139 140 #define REG_ODT_TIME_LOW_ADDR 0x1428 141 #define REG_ODT_ON_CTL_RD_OFFS 12 142 #define REG_ODT_OFF_CTL_RD_OFFS 16 143 #define REG_SDRAM_ERROR_ADDR 0x1454 144 #define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474 145 #define REG_ODT_TIME_HIGH_ADDR 0x147C 146 147 #define REG_SDRAM_INIT_CTRL_ADDR 0x1480 148 #define REG_SDRAM_INIT_CTRL_OFFS 0 149 #define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2 150 #define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3 151 152 #define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494 153 154 #define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498 155 /*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */ 156 #define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0 157 #define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3 158 159 #define REG_DUNIT_ODT_CTRL_ADDR 0x149C 160 #define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8 161 #define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9 162 163 #define REG_DRAM_FIFO_CTRL_ADDR 0x14A0 164 165 #define REG_DRAM_AXI_CTRL_ADDR 0x14A8 166 #define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0 167 168 #define REG_METAL_MASK_ADDR 0x14B0 169 #define REG_METAL_MASK_MASK 0xDFFFFFFF 170 #define REG_METAL_MASK_RETRY_OFFS 0 171 172 #define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0 173 174 #define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4 175 #define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8 176 #define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC 177 178 #define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8 179 180 #define REG_CS_SIZE_SCRATCH_ADDR 0x1504 181 #define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520 182 #define REG_DDR_IO_ADDR 0x1524 183 #define REG_DDR_IO_CLK_RATIO_OFFS 15 184 185 #define REG_DFS_ADDR 0x1528 186 #define REG_DFS_DLLNEXTSTATE_OFFS 0 187 #define REG_DFS_BLOCK_OFFS 1 188 #define REG_DFS_SR_OFFS 2 189 #define REG_DFS_ATSR_OFFS 3 190 #define REG_DFS_RECONF_OFFS 4 191 #define REG_DFS_CL_NEXT_STATE_OFFS 8 192 #define REG_DFS_CL_NEXT_STATE_MASK 0xF 193 #define REG_DFS_CWL_NEXT_STATE_OFFS 12 194 #define REG_DFS_CWL_NEXT_STATE_MASK 0x7 195 196 #define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 197 #define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F 198 #define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8 199 200 #define REG_READ_DATA_READY_DELAYS_ADDR 0x153C 201 #define REG_READ_DATA_READY_DELAYS_MASK 0x1F 202 #define REG_READ_DATA_READY_DELAYS_OFFS 8 203 204 #define START_BURST_IN_ADDR 1 205 206 #define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488 207 #define REG_DRAM_TRAINING_ADDR 0x15B0 208 #define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0 209 #define REG_DRAM_TRAINING_PATTERNS_OFFS 4 210 #define REG_DRAM_TRAINING_MED_FREQ_OFFS 2 211 #define REG_DRAM_TRAINING_WL_OFFS 3 212 #define REG_DRAM_TRAINING_RL_OFFS 6 213 #define REG_DRAM_TRAINING_DQS_RX_OFFS 15 214 #define REG_DRAM_TRAINING_DQS_TX_OFFS 16 215 #define REG_DRAM_TRAINING_CS_OFFS 20 216 #define REG_DRAM_TRAINING_RETEST_OFFS 24 217 #define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27 218 #define REG_DRAM_TRAINING_DFS_REQ_OFFS 29 219 #define REG_DRAM_TRAINING_ERROR_OFFS 30 220 #define REG_DRAM_TRAINING_AUTO_OFFS 31 221 #define REG_DRAM_TRAINING_RETEST_PAR 0x3 222 #define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF 223 #define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF 224 #define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000 225 226 #define REG_DRAM_TRAINING_1_ADDR 0x15B4 227 #define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16 228 229 #define REG_DRAM_TRAINING_2_ADDR 0x15B8 230 #define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17 231 #define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4 232 #define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3 233 #define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 234 #define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1 235 #define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0 236 237 #define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC 238 #define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3 239 240 #define REG_TRAINING_DEBUG_2_ADDR 0x15C4 241 #define REG_TRAINING_DEBUG_2_OFFS 16 242 #define REG_TRAINING_DEBUG_2_MASK 0x3 243 244 #define REG_TRAINING_DEBUG_3_ADDR 0x15C8 245 #define REG_TRAINING_DEBUG_3_OFFS 3 246 #define REG_TRAINING_DEBUG_3_MASK 0x7 247 248 #define MR_CS_ADDR_OFFS 4 249 250 #define REG_DDR3_MR0_ADDR 0x15D0 251 #define REG_DDR3_MR0_CS_ADDR 0x1870 252 #define REG_DDR3_MR0_CL_MASK 0x74 253 #define REG_DDR3_MR0_CL_OFFS 2 254 #define REG_DDR3_MR0_CL_HIGH_OFFS 3 255 #define CL_MASK 0xF 256 257 #define REG_DDR3_MR1_ADDR 0x15D4 258 #define REG_DDR3_MR1_CS_ADDR 0x1874 259 #define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB 260 #define REG_DDR3_MR1_DLL_ENA_OFFS 0 261 #define REG_DDR3_MR1_RTT_DISABLED 0x0 262 #define REG_DDR3_MR1_RTT_RZQ2 0x40 263 #define REG_DDR3_MR1_RTT_RZQ4 0x2 264 #define REG_DDR3_MR1_RTT_RZQ6 0x42 265 #define REG_DDR3_MR1_RTT_RZQ8 0x202 266 #define REG_DDR3_MR1_RTT_RZQ12 0x4 267 #define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */ 268 #define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */ 269 #define REG_DDR3_MR1_WL_ENA_OFFS 7 270 #define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */ 271 #define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB 272 273 #define REG_DDR3_MR2_ADDR 0x15D8 274 #define REG_DDR3_MR2_CS_ADDR 0x1878 275 #define REG_DDR3_MR2_CWL_OFFS 3 276 #define REG_DDR3_MR2_CWL_MASK 0x7 277 #define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF 278 #define REG_DDR3_MR3_ADDR 0x15DC 279 #define REG_DDR3_MR3_CS_ADDR 0x187C 280 281 #define REG_DDR3_RANK_CTRL_ADDR 0x15E0 282 #define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF 283 #define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4 284 285 #define REG_ZQC_CONF_ADDR 0x15E4 286 287 #define REG_DRAM_PHY_CONFIG_ADDR 0x15EC 288 #define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF 289 290 #define REG_ODPG_CNTRL_ADDR 0x1600 291 #define REG_ODPG_CNTRL_OFFS 21 292 293 #define REG_PHY_LOCK_MASK_ADDR 0x1670 294 #define REG_PHY_LOCK_MASK_MASK 0xFFFFF000 295 296 #define REG_PHY_LOCK_STATUS_ADDR 0x1674 297 #define REG_PHY_LOCK_STATUS_LOCK_OFFS 9 298 #define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF 299 #define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF 300 301 #define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0 302 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000 303 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000 304 #define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000 305 #define REG_PHY_BC_OFFS 27 306 #define REG_PHY_CNTRL_OFFS 26 307 #define REG_PHY_CS_OFFS 16 308 #define REG_PHY_DQS_REF_DLY_OFFS 10 309 #define REG_PHY_PHASE_OFFS 8 310 #define REG_PHY_PUP_OFFS 22 311 312 #define REG_TRAINING_WL_ADDR 0x16AC 313 #define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC 314 #define REG_TRAINING_WL_UPD_OFFS 2 315 #define REG_TRAINING_WL_CS_DONE_OFFS 3 316 #define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F 317 #define REG_TRAINING_WL_1TO1 0x50 318 #define REG_TRAINING_WL_2TO1 0x10 319 #define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000 320 #define REG_TRAINING_WL_RESULTS_MASK 0x000001FF 321 #define REG_TRAINING_WL_RESULTS_OFFS 20 322 323 #define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0 324 #define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15 325 #define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F 326 /* DLB*/ 327 #define REG_STATIC_DRAM_DLB_CONTROL 0x1700 328 #define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704 329 #define DLB_AGING_REGISTER 0x1708 330 #define DLB_EVICTION_CONTROL_REG 0x170c 331 #define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710 332 333 #define DLB_ENABLE 0x1 334 #define DLB_WRITE_COALESING (0x1 << 2) 335 #define DLB_AXI_PREFETCH_EN (0x1 << 3) 336 #define DLB_MBUS_PREFETCH_EN (0x1 << 4) 337 #define PREFETCH_NLNSZTR (0x1 << 6) 338 339 /* CPU */ 340 #define REG_BOOTROM_ROUTINE_ADDR 0x182D0 341 #define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12 342 343 #define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488 344 #define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16 345 #define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF 346 #define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488 347 348 #define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700 349 350 #define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704 351 #define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708 352 353 #define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C 354 #define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF 355 #define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8 356 357 #define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710 358 359 #define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718 360 #define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8 361 362 #define REG_CPU_PLL_CTRL_0_ADDR 0x1871C 363 #define REG_CPU_PLL_STATUS_0_ADDR 0x18724 364 #define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740 365 #define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744 366 #define REG_DDRPHY_APLL_CTRL_ADDR 0x18780 367 368 #define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784 369 370 #define REG_SFABRIC_CLK_CTRL_ADDR 0x20858 371 #define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8 372 373 /* DRAM Windows */ 374 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 375 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 376 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 377 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 378 #define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184 379 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 380 381 /* SRAM */ 382 #define REG_CDI_CONFIG_ADDR 0x20220 383 #define REG_SRAM_WINDOW_0_ADDR 0x20240 384 #define REG_SRAM_WINDOW_0_ENA_OFFS 0 385 #define REG_SRAM_WINDOW_1_ADDR 0x20244 386 #define REG_SRAM_L2_ENA_ADDR 0x8500 387 #define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC 388 389 /* PMU */ 390 #define REG_PMU_I_F_CTRL_ADDR 0x1C090 391 #define REG_PMU_DUNIT_BLK_OFFS 16 392 #define REG_PMU_DUNIT_RFRS_OFFS 20 393 #define REG_PMU_DUNIT_ACK_OFFS 24 394 395 /* MBUS*/ 396 #define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420) 397 #define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424) 398 #define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428) 399 #define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c) 400 401 #define REG_PM_STAT_MASK_ADDR 0x2210C 402 #define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16 403 404 #define REG_PM_EVENT_STAT_MASK_ADDR 0x22120 405 #define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17 406 407 #define REG_PM_CTRL_CONFIG_ADDR 0x22104 408 #define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18 409 410 #define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4 411 #define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18 412 413 /* Controller revision info */ 414 #define PCI_CLASS_CODE_AND_REVISION_ID 0x008 415 #define PCCRIR_REVID_OFFS 0 /* Revision ID */ 416 #define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) 417 418 /* Power Management Clock Gating Control Register */ 419 #define MV_PEX_IF_REGS_OFFSET(if) \ 420 (if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \ 421 : (0x42000 + ((if) % 8) * 0x40000)) 422 #define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit)) 423 #define POWER_MNG_CTRL_REG 0x18220 424 #define PEX_DEVICE_AND_VENDOR_ID 0x000 425 #define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg)) 426 #define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port))) 427 #define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 428 #define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port)) 429 #define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port)) 430 431 /* TWSI */ 432 #define TWSI_DATA_ADDR_MASK 0x7 433 #define TWSI_DATA_ADDR_OFFS 1 434 435 /* General */ 436 #define MAX_CS 4 437 438 /* Frequencies */ 439 #define FAB_OPT 21 440 #define CLK_CPU 12 441 #define CLK_VCO (2 * CLK_CPU) 442 #define CLK_DDR 12 443 444 /* Cpu Frequencies: */ 445 #define CLK_CPU_1000 0 446 #define CLK_CPU_1066 1 447 #define CLK_CPU_1200 2 448 #define CLK_CPU_1333 3 449 #define CLK_CPU_1500 4 450 #define CLK_CPU_1666 5 451 #define CLK_CPU_1800 6 452 #define CLK_CPU_2000 7 453 #define CLK_CPU_600 8 454 #define CLK_CPU_667 9 455 #define CLK_CPU_800 0xa 456 457 /* Extra Cpu Frequencies: */ 458 #define CLK_CPU_1600 11 459 #define CLK_CPU_2133 12 460 #define CLK_CPU_2200 13 461 #define CLK_CPU_2400 14 462 463 /* DDR3 Frequencies: */ 464 #define DDR_100 0 465 #define DDR_300 1 466 #define DDR_333 1 467 #define DDR_360 2 468 #define DDR_400 3 469 #define DDR_444 4 470 #define DDR_500 5 471 #define DDR_533 6 472 #define DDR_600 7 473 #define DDR_640 8 474 #define DDR_666 8 475 #define DDR_720 9 476 #define DDR_750 9 477 #define DDR_800 10 478 #define DDR_833 11 479 #define DDR_HCLK 20 480 #define DDR_S 12 481 #define DDR_S_1TO1 13 482 #define MARGIN_FREQ DDR_400 483 #define DFS_MARGIN DDR_100 484 485 #define ODT_OPT 16 486 #define ODT20 0x200 487 #define ODT30 0x204 488 #define ODT40 0x44 489 #define ODT120 0x40 490 #define ODT120D 0x400 491 492 #define MRS_DELAY 100 493 494 #define SDRAM_WL_SW_OFFS 0x100 495 #define SDRAM_RL_OFFS 0x0 496 #define SDRAM_PBS_I_OFFS 0x140 497 #define SDRAM_PBS_II_OFFS 0x180 498 #define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS) 499 #define SDRAM_PBS_TX_OFFS 0x180 500 #define SDRAM_PBS_TX_DM_OFFS 576 501 #define SDRAM_DQS_RX_OFFS 1024 502 #define SDRAM_DQS_TX_OFFS 2048 503 #define SDRAM_DQS_RX_SPECIAL_OFFS 5120 504 505 #define LEN_STD_PATTERN 16 506 #define LEN_KILLER_PATTERN 128 507 #define LEN_SPECIAL_PATTERN 128 508 #define LEN_PBS_PATTERN 16 509 510 #endif /* __DDR3_AXP_H */ 511