1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _XOR_REGS_h 8 #define _XOR_REGS_h 9 10 /* 11 * For controllers that have two XOR units, then chans 2 & 3 will be 12 * mapped to channels 0 & 1 of unit 1 13 */ 14 #define XOR_UNIT(chan) ((chan) >> 1) 15 #define XOR_CHAN(chan) ((chan) & 1) 16 17 #define MV_XOR_REGS_OFFSET(unit) (0x60900) 18 #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) 19 20 /* XOR Engine Control Register Map */ 21 #define XOR_CHANNEL_ARBITER_REG(unit) (MV_XOR_REGS_BASE(unit)) 22 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 23 (0x10 + ((chan) * 4))) 24 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 25 (0x20 + ((chan) * 4))) 26 27 /* XOR Engine Interrupt Register Map */ 28 #define XOR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x30)) 29 #define XOR_MASK_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x40)) 30 #define XOR_ERROR_CAUSE_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x50)) 31 #define XOR_ERROR_ADDR_REG(unit) (MV_XOR_REGS_BASE(unit)+(0x60)) 32 33 /* XOR Engine Descriptor Register Map */ 34 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 35 (0x200 + ((chan) * 4))) 36 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 37 (0x210 + ((chan) * 4))) 38 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 39 (0x220 + ((chan) * 4))) 40 41 /* XOR Engine ECC/Mem_init Register Map */ 42 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 43 (0x2b0 + ((chan) * 4))) 44 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 45 (0x2c0 + ((chan) * 4))) 46 #define XOR_TIMER_MODE_CTRL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d0)) 47 #define XOR_TIMER_MODE_INIT_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d4)) 48 #define XOR_TIMER_MODE_CURR_VAL_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2d8)) 49 #define XOR_INIT_VAL_LOW_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e0)) 50 #define XOR_INIT_VAL_HIGH_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x2e4)) 51 52 /* XOR Engine Debug Register Map */ 53 #define XOR_DEBUG_REG(unit) (MV_XOR_REGS_BASE(unit) + (0x70)) 54 55 /* XOR register fileds */ 56 57 /* XOR Engine Channel Arbiter Register */ 58 #define XECAR_SLICE_OFFS(slice_num) (slice_num) 59 #define XECAR_SLICE_MASK(slice_num) (1 << (XECAR_SLICE_OFFS(slice_num))) 60 61 /* XOR Engine [0..1] Configuration Registers */ 62 #define XEXCR_OPERATION_MODE_OFFS (0) 63 #define XEXCR_OPERATION_MODE_MASK (7 << XEXCR_OPERATION_MODE_OFFS) 64 #define XEXCR_OPERATION_MODE_XOR (0 << XEXCR_OPERATION_MODE_OFFS) 65 #define XEXCR_OPERATION_MODE_CRC (1 << XEXCR_OPERATION_MODE_OFFS) 66 #define XEXCR_OPERATION_MODE_DMA (2 << XEXCR_OPERATION_MODE_OFFS) 67 #define XEXCR_OPERATION_MODE_ECC (3 << XEXCR_OPERATION_MODE_OFFS) 68 #define XEXCR_OPERATION_MODE_MEM_INIT (4 << XEXCR_OPERATION_MODE_OFFS) 69 70 #define XEXCR_SRC_BURST_LIMIT_OFFS (4) 71 #define XEXCR_SRC_BURST_LIMIT_MASK (7 << XEXCR_SRC_BURST_LIMIT_OFFS) 72 #define XEXCR_DST_BURST_LIMIT_OFFS (8) 73 #define XEXCR_DST_BURST_LIMIT_MASK (7 << XEXCR_DST_BURST_LIMIT_OFFS) 74 #define XEXCR_DRD_RES_SWP_OFFS (12) 75 #define XEXCR_DRD_RES_SWP_MASK (1 << XEXCR_DRD_RES_SWP_OFFS) 76 #define XEXCR_DWR_REQ_SWP_OFFS (13) 77 #define XEXCR_DWR_REQ_SWP_MASK (1 << XEXCR_DWR_REQ_SWP_OFFS) 78 #define XEXCR_DES_SWP_OFFS (14) 79 #define XEXCR_DES_SWP_MASK (1 << XEXCR_DES_SWP_OFFS) 80 #define XEXCR_REG_ACC_PROTECT_OFFS (15) 81 #define XEXCR_REG_ACC_PROTECT_MASK (1 << XEXCR_REG_ACC_PROTECT_OFFS) 82 83 /* XOR Engine [0..1] Activation Registers */ 84 #define XEXACTR_XESTART_OFFS (0) 85 #define XEXACTR_XESTART_MASK (1 << XEXACTR_XESTART_OFFS) 86 #define XEXACTR_XESTOP_OFFS (1) 87 #define XEXACTR_XESTOP_MASK (1 << XEXACTR_XESTOP_OFFS) 88 #define XEXACTR_XEPAUSE_OFFS (2) 89 #define XEXACTR_XEPAUSE_MASK (1 << XEXACTR_XEPAUSE_OFFS) 90 #define XEXACTR_XERESTART_OFFS (3) 91 #define XEXACTR_XERESTART_MASK (1 << XEXACTR_XERESTART_OFFS) 92 #define XEXACTR_XESTATUS_OFFS (4) 93 #define XEXACTR_XESTATUS_MASK (3 << XEXACTR_XESTATUS_OFFS) 94 #define XEXACTR_XESTATUS_IDLE (0 << XEXACTR_XESTATUS_OFFS) 95 #define XEXACTR_XESTATUS_ACTIVE (1 << XEXACTR_XESTATUS_OFFS) 96 #define XEXACTR_XESTATUS_PAUSED (2 << XEXACTR_XESTATUS_OFFS) 97 98 /* XOR Engine Interrupt Cause Register (XEICR) */ 99 #define XEICR_CHAN_OFFS 16 100 #define XEICR_CAUSE_OFFS(chan) (chan * XEICR_CHAN_OFFS) 101 #define XEICR_CAUSE_MASK(chan, cause) (1 << (cause + XEICR_CAUSE_OFFS(chan))) 102 #define XEICR_COMP_MASK_ALL 0x000f000f 103 #define XEICR_COMP_MASK(chan) (0x000f << XEICR_CAUSE_OFFS(chan)) 104 #define XEICR_ERR_MASK 0x03800380 105 106 /* XOR Engine Error Cause Register (XEECR) */ 107 #define XEECR_ERR_TYPE_OFFS 0 108 #define XEECR_ERR_TYPE_MASK (0x1f << XEECR_ERR_TYPE_OFFS) 109 110 /* XOR Engine Error Address Register (XEEAR) */ 111 #define XEEAR_ERR_ADDR_OFFS (0) 112 #define XEEAR_ERR_ADDR_MASK (0xffffffff << XEEAR_ERR_ADDR_OFFS) 113 114 /* XOR Engine [0..1] Next Descriptor Pointer Register */ 115 #define XEXNDPR_NEXT_DESC_PTR_OFFS (0) 116 #define XEXNDPR_NEXT_DESC_PTR_MASK (0xffffffff << \ 117 XEXNDPR_NEXT_DESC_PTR_OFFS) 118 119 /* XOR Engine [0..1] Current Descriptor Pointer Register */ 120 #define XEXCDPR_CURRENT_DESC_PTR_OFFS (0) 121 #define XEXCDPR_CURRENT_DESC_PTR_MASK (0xffffffff << \ 122 XEXCDPR_CURRENT_DESC_PTR_OFFS) 123 124 /* XOR Engine [0..1] Byte Count Register */ 125 #define XEXBCR_BYTE_CNT_OFFS (0) 126 #define XEXBCR_BYTE_CNT_MASK (0xffffffff << XEXBCR_BYTE_CNT_OFFS) 127 128 /* XOR Engine [0..1] Destination Pointer Register */ 129 #define XEXDPR_DST_PTR_OFFS (0) 130 #define XEXDPR_DST_PTR_MASK (0xffffffff << XEXDPR_DST_PTR_OFFS) 131 #define XEXDPR_DST_PTR_XOR_MASK (0x3f) 132 #define XEXDPR_DST_PTR_DMA_MASK (0x1f) 133 #define XEXDPR_DST_PTR_CRC_MASK (0x1f) 134 135 /* XOR Engine[0..1] Block Size Registers */ 136 #define XEXBSR_BLOCK_SIZE_OFFS (0) 137 #define XEXBSR_BLOCK_SIZE_MASK (0xffffffff << XEXBSR_BLOCK_SIZE_OFFS) 138 #define XEXBSR_BLOCK_SIZE_MIN_VALUE (128) 139 #define XEXBSR_BLOCK_SIZE_MAX_VALUE (0xffffffff) 140 141 /* XOR Engine Timer Mode Control Register (XETMCR) */ 142 #define XETMCR_TIMER_EN_OFFS (0) 143 #define XETMCR_TIMER_EN_MASK (1 << XETMCR_TIMER_EN_OFFS) 144 #define XETMCR_TIMER_EN_ENABLE (1 << XETMCR_TIMER_EN_OFFS) 145 #define XETMCR_TIMER_EN_DISABLE (0 << XETMCR_TIMER_EN_OFFS) 146 #define XETMCR_SECTION_SIZE_CTRL_OFFS (8) 147 #define XETMCR_SECTION_SIZE_CTRL_MASK (0x1f << XETMCR_SECTION_SIZE_CTRL_OFFS) 148 #define XETMCR_SECTION_SIZE_MIN_VALUE (7) 149 #define XETMCR_SECTION_SIZE_MAX_VALUE (31) 150 151 /* XOR Engine Timer Mode Initial Value Register (XETMIVR) */ 152 #define XETMIVR_TIMER_INIT_VAL_OFFS (0) 153 #define XETMIVR_TIMER_INIT_VAL_MASK (0xffffffff << \ 154 XETMIVR_TIMER_INIT_VAL_OFFS) 155 156 /* XOR Engine Timer Mode Current Value Register (XETMCVR) */ 157 #define XETMCVR_TIMER_CRNT_VAL_OFFS (0) 158 #define XETMCVR_TIMER_CRNT_VAL_MASK (0xffffffff << \ 159 XETMCVR_TIMER_CRNT_VAL_OFFS) 160 161 /* XOR Engine Initial Value Register Low (XEIVRL) */ 162 #define XEIVRL_INIT_VAL_L_OFFS (0) 163 #define XEIVRL_INIT_VAL_L_MASK (0xffffffff << XEIVRL_INIT_VAL_L_OFFS) 164 165 /* XOR Engine Initial Value Register High (XEIVRH) */ 166 #define XEIVRH_INIT_VAL_H_OFFS (0) 167 #define XEIVRH_INIT_VAL_H_MASK (0xffffffff << XEIVRH_INIT_VAL_H_OFFS) 168 169 /* XOR Engine Debug Register (XEDBR) */ 170 #define XEDBR_PARITY_ERR_INSR_OFFS (0) 171 #define XEDBR_PARITY_ERR_INSR_MASK (1 << XEDBR_PARITY_ERR_INSR_OFFS) 172 #define XEDBR_XBAR_ERR_INSR_OFFS (1) 173 #define XEDBR_XBAR_ERR_INSR_MASK (1 << XEDBR_XBAR_ERR_INSR_OFFS) 174 175 /* XOR Engine address decode registers. */ 176 /* Maximum address decode windows */ 177 #define XOR_MAX_ADDR_DEC_WIN 8 178 /* Maximum address arbiter windows */ 179 #define XOR_MAX_REMAP_WIN 4 180 181 /* XOR Engine Address Decoding Register Map */ 182 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ 183 (0x240 + ((chan) * 4))) 184 #define XOR_BASE_ADDR_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 185 (0x250 + ((win_num) * 4))) 186 #define XOR_SIZE_MASK_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 187 (0x270 + ((win_num) * 4))) 188 #define XOR_HIGH_ADDR_REMAP_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 189 (0x290 + ((win_num) * 4))) 190 #define XOR_ADDR_OVRD_REG(unit, win_num) (MV_XOR_REGS_BASE(unit) + \ 191 (0x2a0 + ((win_num) * 4))) 192 193 /* XOR Engine [0..1] Window Control Registers */ 194 #define XEXWCR_WIN_EN_OFFS(win_num) (win_num) 195 #define XEXWCR_WIN_EN_MASK(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 196 #define XEXWCR_WIN_EN_ENABLE(win_num) (1 << (XEXWCR_WIN_EN_OFFS(win_num))) 197 #define XEXWCR_WIN_EN_DISABLE(win_num) (0 << (XEXWCR_WIN_EN_OFFS(win_num))) 198 199 #define XEXWCR_WIN_ACC_OFFS(win_num) ((2 * win_num) + 16) 200 #define XEXWCR_WIN_ACC_MASK(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 201 #define XEXWCR_WIN_ACC_NO_ACC(win_num) (0 << (XEXWCR_WIN_ACC_OFFS(win_num))) 202 #define XEXWCR_WIN_ACC_RO(win_num) (1 << (XEXWCR_WIN_ACC_OFFS(win_num))) 203 #define XEXWCR_WIN_ACC_RW(win_num) (3 << (XEXWCR_WIN_ACC_OFFS(win_num))) 204 205 /* XOR Engine Base Address Registers (XEBARx) */ 206 #define XEBARX_TARGET_OFFS (0) 207 #define XEBARX_TARGET_MASK (0xf << XEBARX_TARGET_OFFS) 208 #define XEBARX_ATTR_OFFS (8) 209 #define XEBARX_ATTR_MASK (0xff << XEBARX_ATTR_OFFS) 210 #define XEBARX_BASE_OFFS (16) 211 #define XEBARX_BASE_MASK (0xffff << XEBARX_BASE_OFFS) 212 213 /* XOR Engine Size Mask Registers (XESMRx) */ 214 #define XESMRX_SIZE_MASK_OFFS (16) 215 #define XESMRX_SIZE_MASK_MASK (0xffff << XESMRX_SIZE_MASK_OFFS) 216 #define XOR_WIN_SIZE_ALIGN _64K 217 218 /* XOR Engine High Address Remap Register (XEHARRx1) */ 219 #define XEHARRX_REMAP_OFFS (0) 220 #define XEHARRX_REMAP_MASK (0xffffffff << XEHARRX_REMAP_OFFS) 221 222 #define XOR_OVERRIDE_CTRL_REG(chan) (MV_XOR_REGS_BASE(XOR_UNIT(chan)) + \ 223 (0x2a0 + ((XOR_CHAN(chan)) * 4))) 224 225 /* XOR Engine [0..1] Address Override Control Register */ 226 #define XEXAOCR_OVR_EN_OFFS(target) (3 * target) 227 #define XEXAOCR_OVR_EN_MASK(target) (1 << (XEXAOCR_OVR_EN_OFFS(target))) 228 #define XEXAOCR_OVR_PTR_OFFS(target) ((3 * target) + 1) 229 #define XEXAOCR_OVR_PTR_MASK(target) (3 << (XEXAOCR_OVR_PTR_OFFS(target))) 230 #define XEXAOCR_OVR_BAR(win_num, target) (win_num << \ 231 (XEXAOCR_OVR_PTR_OFFS(target))) 232 233 /* Maximum address override windows */ 234 #define XOR_MAX_OVERRIDE_WIN 4 235 236 #endif /* _XOR_REGS_h */ 237