1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _XOR_H 7 #define _XOR_H 8 9 #define SRAM_BASE 0x40000000 10 11 #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ 12 #define MV_XOR_MAX_CHAN 4 /* total channels for all units */ 13 #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ 14 15 #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0)) 16 17 /* 18 * This structure describes address space window. Window base can be 19 * 64 bit, window size up to 4GB 20 */ 21 struct addr_win { 22 u32 base_low; /* 32bit base low */ 23 u32 base_high; /* 32bit base high */ 24 u32 size; /* 32bit size */ 25 }; 26 27 /* This structure describes SoC units address decode window */ 28 struct unit_win_info { 29 struct addr_win addr_win; /* An address window */ 30 int enable; /* Address decode window is enabled/disabled */ 31 u8 attrib; /* chip select attributes */ 32 u8 target_id; /* Target Id of this MV_TARGET */ 33 }; 34 35 /* 36 * This enumerator describes the type of functionality the XOR channel 37 * can have while using the same data structures. 38 */ 39 enum xor_type { 40 MV_XOR, /* XOR channel functions as XOR accelerator */ 41 MV_DMA, /* XOR channel functions as IDMA channel */ 42 MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 43 }; 44 45 enum mv_state { 46 MV_IDLE, 47 MV_ACTIVE, 48 MV_PAUSED, 49 MV_UNDEFINED_STATE 50 }; 51 52 /* 53 * This enumerator describes the set of commands that can be applied on 54 * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 55 * status (see MV_STATE enumerator) 56 * 57 * Start can be applied only when status is IDLE 58 * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 59 * Pause can be applied only when status is ACTIVE 60 * Restart can be applied only when status is PAUSED 61 */ 62 enum mv_command { 63 MV_START, /* Start */ 64 MV_STOP, /* Stop */ 65 MV_PAUSE, /* Pause */ 66 MV_RESTART /* Restart */ 67 }; 68 69 enum xor_override_target { 70 SRC_ADDR0, /* Source Address #0 Control */ 71 SRC_ADDR1, /* Source Address #1 Control */ 72 SRC_ADDR2, /* Source Address #2 Control */ 73 SRC_ADDR3, /* Source Address #3 Control */ 74 SRC_ADDR4, /* Source Address #4 Control */ 75 SRC_ADDR5, /* Source Address #5 Control */ 76 SRC_ADDR6, /* Source Address #6 Control */ 77 SRC_ADDR7, /* Source Address #7 Control */ 78 XOR_DST_ADDR, /* Destination Address Control */ 79 XOR_NEXT_DESC /* Next Descriptor Address Control */ 80 }; 81 82 enum mv_state mv_xor_state_get(u32 chan); 83 void mv_xor_hal_init(u32 xor_chan_num); 84 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl); 85 int mv_xor_command_set(u32 chan, enum mv_command command); 86 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num, 87 int enable); 88 int mv_xor_transfer(u32 chan, enum xor_type type, u32 xor_chain_ptr); 89 90 #endif 91