1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6 #ifndef _MV_DDR_TRAINING_DB_H 7 #define _MV_DDR_TRAINING_DB_H 8 9 #include "mv_ddr_topology.h" 10 11 /* in ns */ 12 #define TREFI_LOW 7800 13 #define TREFI_HIGH 3900 14 15 enum mv_ddr_page_size { 16 MV_DDR_PAGE_SIZE_1K = 1, 17 MV_DDR_PAGE_SIZE_2K 18 }; 19 20 struct mv_ddr_page_element { 21 /* 8-bit bus width page size */ 22 enum mv_ddr_page_size page_size_8bit; 23 /* 16-bit bus width page size */ 24 enum mv_ddr_page_size page_size_16bit; 25 }; 26 27 /* cas latency value per frequency */ 28 struct mv_ddr_cl_val_per_freq { 29 unsigned int cl_val[MV_DDR_FREQ_LAST]; 30 }; 31 32 u32 mv_ddr_rfc_get(u32 mem); 33 unsigned int *mv_ddr_freq_tbl_get(void); 34 u32 mv_ddr_freq_get(enum mv_ddr_freq freq); 35 u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size); 36 unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element); 37 u32 mv_ddr_cl_val_get(u32 index, u32 freq); 38 u32 mv_ddr_cwl_val_get(u32 index, u32 freq); 39 40 #endif /* _MV_DDR_TRAINING_DB_H */ 41