1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _MV_DDR_REGS_H
7 #define _MV_DDR_REGS_H
8 
9 #define GLOB_CTRL_STATUS_REG			0x1030
10 #define TRAINING_TRIGGER_OFFS			0
11 #define TRAINING_TRIGGER_MASK			0x1
12 #define TRAINING_TRIGGER_ENA			1
13 #define TRAINING_DONE_OFFS			1
14 #define TRAINING_DONE_MASK			0x1
15 #define TRAINING_DONE_DONE			1
16 #define TRAINING_DONE_NOT_DONE			0
17 #define TRAINING_RESULT_OFFS			2
18 #define TRAINING_RESULT_MASK			0x1
19 #define TRAINING_RESULT_PASS			0
20 #define TRAINING_RESULT_FAIL			1
21 
22 #define GENERAL_TRAINING_OPCODE_REG		0x1034
23 
24 #define OPCODE_REG0_BASE			0x1038
25 #define OPCODE_REG0_REG(obj)			(OPCODE_REG0_BASE + (obj) * 0x4)
26 
27 #define OPCODE_REG1_BASE			0x10b0
28 #define OPCODE_REG1_REG(obj)			(OPCODE_REG1_BASE + (obj) * 0x4)
29 
30 #define CAL_PHY_BASE				0x10c0
31 #define CAL_PHY_REG(obj)			(CAL_PHY_BASE + (obj) * 0x4)
32 
33 #define WL_DONE_CNTR_REF_REG			0x10f8
34 #define ODPG_WR_RD_MODE_ENA_REG			0x10fc
35 
36 #define SDRAM_CFG_REG				0x1400
37 #define REFRESH_OFFS				0
38 #define REFRESH_MASK				0x3fff
39 #define DRAM_TYPE_OFFS				14
40 #define DRAM_TYPE_MASK				0x1
41 #define BUS_IN_USE_OFFS				15
42 #define BUS_IN_USE_MASK				0x1
43 #define CPU_2DRAM_WR_BUFF_CUT_TH_OFFS		16
44 #define CPU_2DRAM_WR_BUFF_CUT_TH_MASK		0x1
45 #define REG_DIMM_OFFS				17
46 #define REG_DIMM_MASK				0x1
47 #define ECC_OFFS				18
48 #define ECC_MASK				0x1
49 #define IGNORE_ERRORS_OFFS			19
50 #define IGNORE_ERRORS_MASK			0x1
51 #define DRAM_TYPE_HIGH_OFFS			20
52 #define DRAM_TYPE_HIGH_MASK			0x1
53 #define SELF_REFRESH_MODE_OFFS			24
54 #define SELF_REFRESH_MODE_MASK			0x1
55 #define CPU_RD_PER_PROP_OFFS			25
56 #define CPU_RD_PER_PROP_MASK			0x1
57 #define DDR4_EMULATION_OFFS			26
58 #define DDR4_EMULATION_MASK			0x1
59 #define PHY_RF_RST_OFFS				27
60 #define PHY_RF_RST_MASK				0x1
61 #define PUP_RST_DIVIDER_OFFS			28
62 #define PUP_RST_DIVIDER_MASK			0x1
63 #define DATA_PUP_WR_RESET_OFFS			29
64 #define DATA_PUP_WR_RESET_MASK			0x1
65 #define DATA_PUP_RD_RESET_OFFS			30
66 #define DATA_PUP_RD_RESET_MASK			0x1
67 #define DATA_PUP_RD_RESET_ENA			0x0
68 #define DATA_PUP_RD_RESET_DIS			0x1
69 #define IO_BIST_OFFS				31
70 #define DATA_PUP_RD_RESET_MASK			0x1
71 
72 #define DUNIT_CTRL_LOW_REG			0x1404
73 
74 #define SDRAM_TIMING_LOW_REG			0x1408
75 #define SDRAM_TIMING_LOW_TRAS_OFFS		0
76 #define SDRAM_TIMING_LOW_TRAS_MASK		0xf
77 #define SDRAM_TIMING_LOW_TRCD_OFFS		4
78 #define SDRAM_TIMING_LOW_TRCD_MASK		0xf
79 #define SDRAM_TIMING_HIGH_TRCD_OFFS		22
80 #define SDRAM_TIMING_HIGH_TRCD_MASK		0x1
81 #define SDRAM_TIMING_LOW_TRP_OFFS		8
82 #define SDRAM_TIMING_LOW_TRP_MASK		0xf
83 #define SDRAM_TIMING_HIGH_TRP_OFFS		23
84 #define SDRAM_TIMING_HIGH_TRP_MASK		0x1
85 #define SDRAM_TIMING_LOW_TWR_OFFS		12
86 #define SDRAM_TIMING_LOW_TWR_MASK		0xf
87 #define SDRAM_TIMING_LOW_TWTR_OFFS		16
88 #define SDRAM_TIMING_LOW_TWTR_MASK		0xf
89 #define SDRAM_TIMING_LOW_TRAS_HIGH_OFFS		20
90 #define SDRAM_TIMING_LOW_TRAS_HIGH_MASK		0x3
91 #define SDRAM_TIMING_LOW_TRRD_OFFS		24
92 #define SDRAM_TIMING_LOW_TRRD_MASK		0xf
93 #define SDRAM_TIMING_LOW_TRTP_OFFS		28
94 #define SDRAM_TIMING_LOW_TRTP_MASK		0xf
95 
96 #define SDRAM_TIMING_HIGH_REG			0x140c
97 #define SDRAM_TIMING_HIGH_TRFC_OFFS		0
98 #define SDRAM_TIMING_HIGH_TRFC_MASK		0x7f
99 #define SDRAM_TIMING_HIGH_TR2R_OFFS		7
100 #define SDRAM_TIMING_HIGH_TR2R_MASK		0x3
101 #define SDRAM_TIMING_HIGH_TR2W_W2R_OFFS		9
102 #define SDRAM_TIMING_HIGH_TR2W_W2R_MASK		0x3
103 #define SDRAM_TIMING_HIGH_TW2W_OFFS		11
104 #define SDRAM_TIMING_HIGH_TW2W_MASK		0x1f
105 #define SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS	16
106 #define SDRAM_TIMING_HIGH_TRFC_HIGH_MASK	0x7
107 #define SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS	19
108 #define SDRAM_TIMING_HIGH_TR2R_HIGH_MASK	0x7
109 #define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS	22
110 #define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK	0x7
111 #define SDRAM_TIMING_HIGH_TMOD_OFFS		25
112 #define SDRAM_TIMING_HIGH_TMOD_MASK		0xf
113 #define SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS	30
114 #define SDRAM_TIMING_HIGH_TMOD_HIGH_MASK	0x3
115 
116 #define SDRAM_ADDR_CTRL_REG			0x1410
117 #define CS_STRUCT_BASE				0
118 #define CS_STRUCT_OFFS(cs)			(CS_STRUCT_BASE + (cs) * 4)
119 #define CS_STRUCT_MASK				0x3
120 #define CS_SIZE_BASE				2
121 #define CS_SIZE_OFFS(cs)			(CS_SIZE_BASE + (cs) * 4)
122 #define CS_SIZE_MASK				0x3
123 #define CS_SIZE_HIGH_BASE			20
124 #define CS_SIZE_HIGH_OFFS(cs)			(CS_SIZE_HIGH_BASE + (cs))
125 #define CS_SIZE_HIGH_MASK			0x1
126 #define T_FAW_OFFS				24
127 #define T_FAW_MASK				0x7f
128 
129 #define SDRAM_OPEN_PAGES_CTRL_REG		0x1414
130 
131 #define SDRAM_OP_REG				0x1418
132 #define SDRAM_OP_CMD_OFFS			0
133 #define SDRAM_OP_CMD_MASK			0x1f
134 #define SDRAM_OP_CMD_CS_BASE			8
135 #define SDRAM_OP_CMD_CS_OFFS(cs)		(SDRAM_OP_CMD_CS_BASE + (cs))
136 #define SDRAM_OP_CMD_CS_MASK			0x1
137 enum {
138 	CMD_NORMAL,
139 	CMD_PRECHARGE,
140 	CMD_REFRESH,
141 	CMD_DDR3_DDR4_MR0,
142 	CMD_DDR3_DDR4_MR1,
143 	CMD_NOP,
144 	CMD_RES_0X6,
145 	CMD_SELFREFRESH,
146 	CMD_DDR3_DDR4_MR2,
147 	CMD_DDR3_DDR4_MR3,
148 	CMD_ACT_PDE,
149 	CMD_PRE_PDE,
150 	CMD_ZQCL,
151 	CMD_ZQCS,
152 	CMD_CWA,
153 	CMD_RES_0XF,
154 	CMD_DDR4_MR4,
155 	CMD_DDR4_MR5,
156 	CMD_DDR4_MR6,
157 	DDR4_MPR_WR
158 };
159 
160 #define DUNIT_CTRL_HIGH_REG			0x1424
161 #define CPU_INTERJECTION_ENA_OFFS		3
162 #define CPU_INTERJECTION_ENA_MASK		0x1
163 #define CPU_INTERJECTION_ENA_SPLIT_ENA		0
164 #define CPU_INTERJECTION_ENA_SPLIT_DIS		1
165 
166 #define DDR_ODT_TIMING_LOW_REG			0x1428
167 
168 #define DDR_TIMING_REG				0x142c
169 #define DDR_TIMING_TCCD_OFFS			18
170 #define DDR_TIMING_TCCD_MASK			0x7
171 #define DDR_TIMING_TPD_OFFS			0
172 #define DDR_TIMING_TPD_MASK			0xf
173 #define DDR_TIMING_TXPDLL_OFFS			4
174 #define DDR_TIMING_TXPDLL_MASK			0x1f
175 
176 #define DDR_ODT_TIMING_HIGH_REG			0x147c
177 
178 #define SDRAM_INIT_CTRL_REG			0x1480
179 #define DRAM_RESET_MASK_OFFS			1
180 #define DRAM_RESET_MASK_MASK			0x1
181 #define DRAM_RESET_MASK_NORMAL			0
182 #define DRAM_RESET_MASK_MASKED			1
183 
184 #define SDRAM_ODT_CTRL_HIGH_REG			0x1498
185 #define DUNIT_ODT_CTRL_REG			0x149c
186 #define RD_BUFFER_SEL_REG			0x14a4
187 #define AXI_CTRL_REG				0x14a8
188 #define DUNIT_MMASK_REG				0x14b0
189 
190 #define HORZ_SSTL_CAL_MACH_CTRL_REG		0x14c8
191 #define HORZ_POD_CAL_MACH_CTRL_REG		0x17c8
192 #define VERT_SSTL_CAL_MACH_CTRL_REG		0x1dc8
193 #define VERT_POD_CAL_MACH_CTRL_REG		0x1ec8
194 
195 #define MAIN_PADS_CAL_MACH_CTRL_REG		0x14cc
196 #define DYN_PADS_CAL_ENABLE_OFFS		0
197 #define DYN_PADS_CAL_ENABLE_MASK		0x1
198 #define DYN_PADS_CAL_ENABLE_DIS			0
199 #define DYN_PADS_CAL_ENABLE_ENA			1
200 #define PADS_RECAL_OFFS				1
201 #define PADS_RECAL_MASK				0x1
202 #define DYN_PADS_CAL_BLOCK_OFFS			2
203 #define DYN_PADS_CAL_BLOCK_MASK			0x1
204 #define CAL_UPDATE_CTRL_OFFS			3
205 #define CAL_UPDATE_CTRL_MASK			0x3
206 #define CAL_UPDATE_CTRL_INT			1
207 #define CAL_UPDATE_CTRL_EXT			2
208 #define DYN_PADS_CAL_CNTR_OFFS			13
209 #define DYN_PADS_CAL_CNTR_MASK			0x3ffff
210 #define CAL_MACH_STATUS_OFFS			31
211 #define CAL_MACH_STATUS_MASK			0x1
212 #define CAL_MACH_BUSY				0
213 #define CAL_MACH_RDY				1
214 
215 #define DRAM_DLL_TIMING_REG			0x14e0
216 #define DRAM_ZQ_INIT_TIMIMG_REG			0x14e4
217 #define DRAM_ZQ_TIMING_REG			0x14e8
218 
219 #define DRAM_LONG_TIMING_REG			0x14ec
220 #define DDR4_TRRD_L_OFFS			0
221 #define DDR4_TRRD_L_MASK			0xf
222 #define DDR4_TWTR_L_OFFS			4
223 #define DDR4_TWTR_L_MASK			0xf
224 
225 #define DDR_IO_REG				0x1524
226 #define DFS_REG					0x1528
227 
228 #define RD_DATA_SMPL_DLYS_REG			0x1538
229 #define RD_SMPL_DLY_CS_BASE			0
230 #define RD_SMPL_DLY_CS_OFFS(cs)			(RD_SMPL_DLY_CS_BASE + (cs) * 8)
231 #define RD_SMPL_DLY_CS_MASK			0x1f
232 
233 #define RD_DATA_RDY_DLYS_REG			0x153c
234 #define RD_RDY_DLY_CS_BASE			0
235 #define RD_RDY_DLY_CS_OFFS(cs)			(RD_RDY_DLY_CS_BASE + (cs) * 8)
236 #define RD_RDY_DLY_CS_MASK			0x1f
237 
238 #define TRAINING_REG				0x15b0
239 #define TRN_START_OFFS				31
240 #define TRN_START_MASK				0x1
241 #define TRN_START_ENA				1
242 #define TRN_START_DIS				0
243 
244 #define TRAINING_SW_1_REG			0x15b4
245 
246 #define TRAINING_SW_2_REG			0x15b8
247 #define TRAINING_ECC_MUX_OFFS			1
248 #define TRAINING_ECC_MUX_MASK			0x1
249 #define TRAINING_ECC_MUX_DIS			0
250 #define TRAINING_ECC_MUX_ENA			1
251 #define TRAINING_SW_OVRD_OFFS			0
252 #define TRAINING_SW_OVRD_MASK			0x1
253 #define TRAINING_SW_OVRD_DIS			0
254 #define TRAINING_SW_OVRD_ENA			1
255 
256 #define TRAINING_PATTERN_BASE_ADDR_REG		0x15bc
257 #define TRAINING_DBG_1_REG			0x15c0
258 #define TRAINING_DBG_2_REG			0x15c4
259 
260 #define TRAINING_DBG_3_REG			0x15c8
261 #define TRN_DBG_RDY_INC_PH_2TO1_BASE		0
262 #define TRN_DBG_RDY_INC_PH_2TO1_OFFS(phase)	(TRN_DBG_RDY_INC_PH_2TO1_BASE + (phase) * 3)
263 #define TRN_DBG_RDY_INC_PH_2TO1_MASK		0x7
264 
265 #define DDR3_RANK_CTRL_REG			0x15e0
266 #define CS_EXIST_BASE				0
267 #define CS_EXIST_OFFS(cs)			(CS_EXIST_BASE + (cs))
268 #define CS_EXIST_MASK				0x1
269 
270 #define ZQC_CFG_REG				0x15e4
271 #define DRAM_PHY_CFG_REG			0x15ec
272 #define ODPG_CTRL_CTRL_REG			0x1600
273 
274 #define ODPG_DATA_CTRL_REG			0x1630
275 #define ODPG_WRBUF_WR_CTRL_OFFS			0
276 #define ODPG_WRBUF_WR_CTRL_MASK			0x1
277 #define ODPG_WRBUF_WR_CTRL_DIS			0
278 #define ODPG_WRBUF_WR_CTRL_ENA			1
279 #define ODPG_WRBUF_RD_CTRL_OFFS			1
280 #define ODPG_WRBUF_RD_CTRL_MASK			0x1
281 #define ODPG_WRBUF_RD_CTRL_DIS			0
282 #define ODPG_WRBUF_RD_CTRL_ENA			1
283 #define ODPG_DATA_CBDEL_OFFS			15
284 #define ODPG_DATA_CBDEL_MASK			0x3f
285 #define ODPG_MODE_OFFS				25
286 #define ODPG_MODE_MASK				0x1
287 #define ODPG_MODE_RX				0
288 #define ODPG_MODE_TX				1
289 #define ODPG_DATA_CS_OFFS			26
290 #define ODPG_DATA_CS_MASK			0x3
291 #define ODPG_DISABLE_OFFS			30
292 #define ODPG_DISABLE_MASK			0x1
293 #define ODPG_DISABLE_DIS			1
294 #define ODPG_ENABLE_OFFS			31
295 #define ODPG_ENABLE_MASK			0x1
296 #define ODPG_ENABLE_ENA				1
297 
298 #define ODPG_DATA_BUFFER_OFFS_REG		0x1638
299 #define ODPG_DATA_BUFFER_SIZE_REG		0x163c
300 #define PHY_LOCK_STATUS_REG			0x1674
301 
302 #define PHY_REG_FILE_ACCESS_REG			0x16a0
303 #define PRFA_DATA_OFFS				0
304 #define PRFA_DATA_MASK				0xffff
305 #define PRFA_REG_NUM_OFFS			16
306 #define PRFA_REG_NUM_MASK			0x3f
307 #define PRFA_PUP_NUM_OFFS			22
308 #define PRFA_PUP_NUM_MASK			0xf
309 #define PRFA_PUP_CTRL_DATA_OFFS			26
310 #define PRFA_PUP_CTRL_DATA_MASK			0x1
311 #define PRFA_PUP_BCAST_WR_ENA_OFFS		27
312 #define PRFA_PUP_BCAST_WR_ENA_MASK		0x1
313 #define PRFA_REG_NUM_HI_OFFS			28
314 #define PRFA_REG_NUM_HI_MASK			0x3
315 #define PRFA_TYPE_OFFS				30
316 #define PRFA_TYPE_MASK				0x1
317 #define PRFA_REQ_OFFS				31
318 #define PRFA_REQ_MASK				0x1
319 #define PRFA_REQ_DIS				0x0
320 #define PRFA_REQ_ENA				0x1
321 
322 #define TRAINING_WL_REG				0x16ac
323 
324 #define ODPG_DATA_WR_ADDR_REG			0x16b0
325 #define ODPG_DATA_WR_ACK_OFFS			0
326 #define ODPG_DATA_WR_ACK_MASK			0x7f
327 #define ODPG_DATA_WR_DATA_OFFS			8
328 #define ODPG_DATA_WR_DATA_MASK			0xff
329 
330 #define ODPG_DATA_WR_DATA_HIGH_REG		0x16b4
331 #define ODPG_DATA_WR_DATA_LOW_REG		0x16b8
332 #define ODPG_DATA_RX_WORD_ERR_ADDR_REG		0x16bc
333 #define ODPG_DATA_RX_WORD_ERR_CNTR_REG		0x16c0
334 #define ODPG_DATA_RX_WORD_ERR_DATA_HIGH_REG	0x16c4
335 #define ODPG_DATA_RX_WORD_ERR_DATA_LOW_REG	0x16c8
336 #define ODPG_DATA_WR_DATA_ERR_REG		0x16cc
337 
338 #define DUAL_DUNIT_CFG_REG			0x16d8
339 #define FC_SAMPLE_STAGES_OFFS			0
340 #define FC_SAMPLE_STAGES_MASK			0x7
341 #define SINGLE_CS_PIN_OFFS			3
342 #define SINGLE_CS_PIN_MASK			0x1
343 #define SINGLE_CS_ENA				1
344 #define TUNING_ACTIVE_SEL_OFFS			6
345 #define TUNING_ACTIVE_SEL_MASK			0x1
346 #define TUNING_ACTIVE_SEL_MC			0
347 #define TUNING_ACTIVE_SEL_TIP			1
348 
349 #define WL_DQS_PATTERN_REG			0x16dc
350 #define ODPG_DONE_STATUS_REG			0x16fc
351 #define ODPG_DONE_STATUS_BIT_OFFS		0
352 #define ODPG_DONE_STATUS_BIT_MASK		0x1
353 #define ODPG_DONE_STATUS_BIT_CLR		0
354 #define ODPG_DONE_STATUS_BIT_SET		1
355 
356 #define RESULT_CTRL_BASE			0x1830
357 #define BLOCK_STATUS_OFFS			25
358 #define BLOCK_STATUS_MASK			0x1
359 #define BLOCK_STATUS_LOCK			1
360 #define BLOCK_STATUS_NOT_LOCKED			0
361 
362 #define MR0_REG					0x15d0
363 #define MR1_REG					0x15d4
364 #define MR2_REG					0x15d8
365 #define MR3_REG					0x15dc
366 #define MRS0_CMD				0x3
367 #define MRS1_CMD				0x4
368 #define MRS2_CMD				0x8
369 #define MRS3_CMD				0x9
370 
371 
372 #define DRAM_PINS_MUX_REG			0x19d4
373 #define CTRL_PINS_MUX_OFFS			0
374 #define CTRL_PINS_MUX_MASK			0x3
375 enum {
376 	DUNIT_DDR3_ON_BOARD,
377 	DUNIT_DDR3_DIMM,
378 	DUNIT_DDR4_ON_BOARD,
379 	DUNIT_DDR4_DIMM
380 };
381 
382 /* ddr phy registers */
383 #define WL_PHY_BASE				0x0
384 #define WL_PHY_REG(cs)				(WL_PHY_BASE + (cs) * 0x4)
385 #define WR_LVL_PH_SEL_OFFS			6
386 #define WR_LVL_PH_SEL_MASK			0x7
387 #define WR_LVL_PH_SEL_PHASE1			1
388 #define WR_LVL_REF_DLY_OFFS			0
389 #define WR_LVL_REF_DLY_MASK			0x1f
390 #define CTRL_CENTER_DLY_OFFS			10
391 #define CTRL_CENTER_DLY_MASK			0x1f
392 #define CTRL_CENTER_DLY_INV_OFFS		15
393 #define CTRL_CENTER_DLY_INV_MASK		0x1
394 
395 #define CTX_PHY_BASE				0x1
396 #define CTX_PHY_REG(cs)				(CTX_PHY_BASE + (cs) * 0x4)
397 
398 #define RL_PHY_BASE				0x2
399 #define RL_PHY_REG(cs)				(RL_PHY_BASE + (cs) * 0x4)
400 #define RL_REF_DLY_OFFS				0
401 #define RL_REF_DLY_MASK				0x1f
402 #define RL_PH_SEL_OFFS				6
403 #define RL_PH_SEL_MASK				0x7
404 
405 #define CRX_PHY_BASE				0x3
406 #define CRX_PHY_REG(cs)				(CRX_PHY_BASE + (cs) * 0x4)
407 
408 #define PHY_CTRL_PHY_REG			0x90
409 #define ADLL_CFG0_PHY_REG			0x92
410 #define ADLL_CFG1_PHY_REG			0x93
411 #define ADLL_CFG2_PHY_REG			0x94
412 #define CMOS_CONFIG_PHY_REG			0xa2
413 #define PAD_ZRI_CAL_PHY_REG			0xa4
414 #define PAD_ODT_CAL_PHY_REG			0xa6
415 #define PAD_CFG_PHY_REG				0xa8
416 #define PAD_PRE_DISABLE_PHY_REG			0xa9
417 #define TEST_ADLL_PHY_REG			0xbf
418 
419 #define VREF_PHY_BASE				0xd0
420 #define VREF_PHY_REG(cs, bit)			(VREF_PHY_BASE + (cs) * 12 + bit)
421 enum {
422 	DQSP_PAD = 4,
423 	DQSN_PAD
424 };
425 
426 #define VREF_BCAST_PHY_BASE			0xdb
427 #define VREF_BCAST_PHY_REG(cs)			(VREF_BCAST_PHY_BASE + (cs) * 12)
428 
429 #define PBS_TX_PHY_BASE				0x10
430 #define PBS_TX_PHY_REG(cs, bit)			(PBS_TX_PHY_BASE + (cs) * 0x10 + (bit))
431 
432 #define PBS_TX_BCAST_PHY_BASE			0x1f
433 #define PBS_TX_BCAST_PHY_REG(cs)		(PBS_TX_BCAST_PHY_BASE + (cs) * 0x10)
434 
435 #define PBS_RX_PHY_BASE				0x50
436 #define PBS_RX_PHY_REG(cs, bit)			(PBS_RX_PHY_BASE + (cs) * 0x10 + (bit))
437 
438 #define PBS_RX_BCAST_PHY_BASE			0x5f
439 #define PBS_RX_BCAST_PHY_REG(cs)		(PBS_RX_BCAST_PHY_BASE + (cs) * 0x10)
440 
441 #define RESULT_PHY_REG				0xc0
442 #define RESULT_PHY_RX_OFFS			5
443 #define RESULT_PHY_TX_OFFS			0
444 
445 
446 #endif /* _MV_DDR_REGS_H */
447