1 /*
2  * Copyright (C) Marvell International Ltd. and its affiliates
3  *
4  * SPDX-License-Identifier:     GPL-2.0
5  */
6 
7 #ifndef _DDR_TOPOLOGY_DEF_H
8 #define _DDR_TOPOLOGY_DEF_H
9 
10 #include "ddr3_training_ip_def.h"
11 #include "ddr3_topology_def.h"
12 
13 #if defined(CONFIG_ARMADA_38X)
14 #include "ddr3_a38x.h"
15 #endif
16 
17 /* bus width in bits */
18 enum hws_bus_width {
19 	BUS_WIDTH_4,
20 	BUS_WIDTH_8,
21 	BUS_WIDTH_16,
22 	BUS_WIDTH_32
23 };
24 
25 enum hws_temperature {
26 	HWS_TEMP_LOW,
27 	HWS_TEMP_NORMAL,
28 	HWS_TEMP_HIGH
29 };
30 
31 enum hws_mem_size {
32 	MEM_512M,
33 	MEM_1G,
34 	MEM_2G,
35 	MEM_4G,
36 	MEM_8G,
37 	MEM_SIZE_LAST
38 };
39 
40 enum hws_timing {
41 	HWS_TIM_DEFAULT,
42 	HWS_TIM_1T,
43 	HWS_TIM_2T
44 };
45 
46 struct bus_params {
47 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
48 	u8 cs_bitmask;
49 
50 	/*
51 	 * mirror enable/disable
52 	 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
53 	 */
54 	int mirror_enable_bitmask;
55 
56 	/* DQS Swap (polarity) - true if enable */
57 	int is_dqs_swap;
58 
59 	/* CK swap (polarity) - true if enable */
60 	int is_ck_swap;
61 };
62 
63 struct if_params {
64 	/* bus configuration */
65 	struct bus_params as_bus_params[MAX_BUS_NUM];
66 
67 	/* Speed Bin Table */
68 	enum hws_speed_bin speed_bin_index;
69 
70 	/* bus width of memory */
71 	enum hws_bus_width bus_width;
72 
73 	/* Bus memory size (MBit) */
74 	enum hws_mem_size memory_size;
75 
76 	/* The DDR frequency for each interfaces */
77 	enum hws_ddr_freq memory_freq;
78 
79 	/*
80 	 * delay CAS Write Latency
81 	 * - 0 for using default value (jedec suggested)
82 	 */
83 	u8 cas_wl;
84 
85 	/*
86 	 * delay CAS Latency
87 	 * - 0 for using default value (jedec suggested)
88 	 */
89 	u8 cas_l;
90 
91 	/* operation temperature */
92 	enum hws_temperature interface_temp;
93 
94 	/* 2T vs 1T mode (by default computed from number of CSs) */
95 	enum hws_timing timing;
96 };
97 
98 struct hws_topology_map {
99 	/* Number of interfaces (default is 12) */
100 	u8 if_act_mask;
101 
102 	/* Controller configuration per interface */
103 	struct if_params interface_params[MAX_INTERFACE_NUM];
104 
105 	/* BUS per interface (default is 4) */
106 	u8 num_of_bus_per_interface;
107 
108 	/* Bit mask for active buses */
109 	u8 bus_act_mask;
110 };
111 
112 /* DDR3 training global configuration parameters */
113 struct tune_train_params {
114 	u32 ck_delay;
115 	u32 ck_delay_16;
116 	u32 p_finger;
117 	u32 n_finger;
118 	u32 phy_reg3_val;
119 };
120 
121 #endif /* _DDR_TOPOLOGY_DEF_H */
122