1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _DDR_TOPOLOGY_DEF_H
7 #define _DDR_TOPOLOGY_DEF_H
8 
9 #include "ddr3_training_ip_def.h"
10 #include "ddr3_topology_def.h"
11 
12 #if defined(CONFIG_ARMADA_38X)
13 #include "ddr3_a38x.h"
14 #endif
15 
16 /* bus width in bits */
17 enum hws_bus_width {
18 	BUS_WIDTH_4,
19 	BUS_WIDTH_8,
20 	BUS_WIDTH_16,
21 	BUS_WIDTH_32
22 };
23 
24 enum hws_temperature {
25 	HWS_TEMP_LOW,
26 	HWS_TEMP_NORMAL,
27 	HWS_TEMP_HIGH
28 };
29 
30 enum hws_mem_size {
31 	MEM_512M,
32 	MEM_1G,
33 	MEM_2G,
34 	MEM_4G,
35 	MEM_8G,
36 	MEM_SIZE_LAST
37 };
38 
39 enum hws_timing {
40 	HWS_TIM_DEFAULT,
41 	HWS_TIM_1T,
42 	HWS_TIM_2T
43 };
44 
45 struct bus_params {
46 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
47 	u8 cs_bitmask;
48 
49 	/*
50 	 * mirror enable/disable
51 	 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
52 	 */
53 	int mirror_enable_bitmask;
54 
55 	/* DQS Swap (polarity) - true if enable */
56 	int is_dqs_swap;
57 
58 	/* CK swap (polarity) - true if enable */
59 	int is_ck_swap;
60 };
61 
62 struct if_params {
63 	/* bus configuration */
64 	struct bus_params as_bus_params[MAX_BUS_NUM];
65 
66 	/* Speed Bin Table */
67 	enum hws_speed_bin speed_bin_index;
68 
69 	/* bus width of memory */
70 	enum hws_bus_width bus_width;
71 
72 	/* Bus memory size (MBit) */
73 	enum hws_mem_size memory_size;
74 
75 	/* The DDR frequency for each interfaces */
76 	enum hws_ddr_freq memory_freq;
77 
78 	/*
79 	 * delay CAS Write Latency
80 	 * - 0 for using default value (jedec suggested)
81 	 */
82 	u8 cas_wl;
83 
84 	/*
85 	 * delay CAS Latency
86 	 * - 0 for using default value (jedec suggested)
87 	 */
88 	u8 cas_l;
89 
90 	/* operation temperature */
91 	enum hws_temperature interface_temp;
92 
93 	/* 2T vs 1T mode (by default computed from number of CSs) */
94 	enum hws_timing timing;
95 };
96 
97 struct hws_topology_map {
98 	/* Number of interfaces (default is 12) */
99 	u8 if_act_mask;
100 
101 	/* Controller configuration per interface */
102 	struct if_params interface_params[MAX_INTERFACE_NUM];
103 
104 	/* BUS per interface (default is 4) */
105 	u8 num_of_bus_per_interface;
106 
107 	/* Bit mask for active buses */
108 	u8 bus_act_mask;
109 };
110 
111 /* DDR3 training global configuration parameters */
112 struct tune_train_params {
113 	u32 ck_delay;
114 	u32 ck_delay_16;
115 	u32 p_finger;
116 	u32 n_finger;
117 	u32 phy_reg3_val;
118 };
119 
120 #endif /* _DDR_TOPOLOGY_DEF_H */
121