1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR_ML_WRAPPER_H 7 #define _DDR_ML_WRAPPER_H 8 9 #include <common.h> 10 #include <i2c.h> 11 #include <spl.h> 12 #include <asm/io.h> 13 #include <asm/arch/cpu.h> 14 #include <asm/arch/soc.h> 15 16 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X) 17 #define INTER_REGS_BASE SOC_REGS_PHY_BASE 18 #endif 19 20 /* 21 * MV_DEBUG_INIT need to be defines, otherwise the output of the 22 * DDR2 training code is not complete and misleading 23 */ 24 #define MV_DEBUG_INIT 25 26 #ifdef MV_DEBUG_INIT 27 #define DEBUG_INIT_S(s) puts(s) 28 #define DEBUG_INIT_D(d, l) printf("%x", d) 29 #define DEBUG_INIT_D_10(d, l) printf("%d", d) 30 #else 31 #define DEBUG_INIT_S(s) 32 #define DEBUG_INIT_D(d, l) 33 #define DEBUG_INIT_D_10(d, l) 34 #endif 35 36 #ifdef MV_DEBUG_INIT_FULL 37 #define DEBUG_INIT_FULL_S(s) puts(s) 38 #define DEBUG_INIT_FULL_D(d, l) printf("%x", d) 39 #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d) 40 #define DEBUG_WR_REG(reg, val) \ 41 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \ 42 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); } 43 #define DEBUG_RD_REG(reg, val) \ 44 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \ 45 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); } 46 #else 47 #define DEBUG_INIT_FULL_S(s) 48 #define DEBUG_INIT_FULL_D(d, l) 49 #define DEBUG_INIT_FULL_D_10(d, l) 50 #define DEBUG_WR_REG(reg, val) 51 #define DEBUG_RD_REG(reg, val) 52 #endif 53 54 #define DEBUG_INIT_FULL_C(s, d, l) \ 55 { DEBUG_INIT_FULL_S(s); \ 56 DEBUG_INIT_FULL_D(d, l); \ 57 DEBUG_INIT_FULL_S("\n"); } 58 #define DEBUG_INIT_C(s, d, l) \ 59 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); } 60 61 /* 62 * Debug (Enable/Disable modules) and Error report 63 */ 64 65 #ifdef BASIC_DEBUG 66 #define MV_DEBUG_WL 67 #define MV_DEBUG_RL 68 #define MV_DEBUG_DQS_RESULTS 69 #endif 70 71 #ifdef FULL_DEBUG 72 #define MV_DEBUG_WL 73 #define MV_DEBUG_RL 74 #define MV_DEBUG_DQS 75 76 #define MV_DEBUG_PBS 77 #define MV_DEBUG_DFS 78 #define MV_DEBUG_MAIN_FULL 79 #define MV_DEBUG_DFS_FULL 80 #define MV_DEBUG_DQS_FULL 81 #define MV_DEBUG_RL_FULL 82 #define MV_DEBUG_WL_FULL 83 #endif 84 85 86 /* The following is a list of Marvell status */ 87 #define MV_ERROR (-1) 88 #define MV_OK (0x00) /* Operation succeeded */ 89 #define MV_FAIL (0x01) /* Operation failed */ 90 #define MV_BAD_VALUE (0x02) /* Illegal value (general) */ 91 #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ 92 #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ 93 #define MV_BAD_PTR (0x05) /* Illegal pointer value */ 94 #define MV_BAD_SIZE (0x06) /* Illegal size */ 95 #define MV_BAD_STATE (0x07) /* Illegal state of state machine */ 96 #define MV_SET_ERROR (0x08) /* Set operation failed */ 97 #define MV_GET_ERROR (0x09) /* Get operation failed */ 98 #define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */ 99 #define MV_NOT_FOUND (0x0b) /* Item not found */ 100 #define MV_NO_MORE (0x0c) /* No more items found */ 101 #define MV_NO_SUCH (0x0d) /* No such item */ 102 #define MV_TIMEOUT (0x0e) /* Time Out */ 103 #define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */ 104 #define MV_NOT_SUPPORTED (0x10) /* This request is not support */ 105 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/ 106 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ 107 #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ 108 #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ 109 #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ 110 #define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ 111 #define MV_HW_ERROR (0x17) /* Hardware error */ 112 #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ 113 #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ 114 #define MV_NOT_READY (0x1a) /* The other side is not ready yet */ 115 #define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */ 116 #define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */ 117 #define MV_NOT_STARTED (0x1d) /* Not started yet */ 118 #define MV_BUSY (0x1e) /* Item is busy. */ 119 #define MV_TERMINATE (0x1f) /* Item terminates it's work. */ 120 #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ 121 #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ 122 #define MV_WRITE_PROTECT (0x22) /* Write protected */ 123 #define MV_INVALID (int)(-1) 124 125 /* 126 * Accessor functions for the registers 127 */ 128 static inline void reg_write(u32 addr, u32 val) 129 { 130 writel(val, INTER_REGS_BASE + addr); 131 } 132 133 static inline u32 reg_read(u32 addr) 134 { 135 return readl(INTER_REGS_BASE + addr); 136 } 137 138 static inline void reg_bit_set(u32 addr, u32 mask) 139 { 140 setbits_le32(INTER_REGS_BASE + addr, mask); 141 } 142 143 static inline void reg_bit_clr(u32 addr, u32 mask) 144 { 145 clrbits_le32(INTER_REGS_BASE + addr, mask); 146 } 147 148 #endif /* _DDR_ML_WRAPPER_H */ 149