1 /*
2  * Copyright (C) Marvell International Ltd. and its affiliates
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 #ifndef _DDR3_TRAINING_IP_PBS_H_
8 #define _DDR3_TRAINING_IP_PBS_H_
9 
10 enum {
11 	EBA_CONFIG,
12 	EEBA_CONFIG,
13 	SBA_CONFIG
14 };
15 
16 enum hws_training_load_op {
17 	TRAINING_LOAD_OPERATION_UNLOAD,
18 	TRAINING_LOAD_OPERATION_LOAD
19 };
20 
21 enum hws_edge {
22 	TRAINING_EDGE_1,
23 	TRAINING_EDGE_2
24 };
25 
26 enum hws_edge_search {
27 	TRAINING_EDGE_MAX,
28 	TRAINING_EDGE_MIN
29 };
30 
31 enum pbs_dir {
32 	PBS_TX_MODE = 0,
33 	PBS_RX_MODE,
34 	NUM_OF_PBS_MODES
35 };
36 
37 int ddr3_tip_pbs_rx(u32 dev_num);
38 int ddr3_tip_print_all_pbs_result(u32 dev_num);
39 int ddr3_tip_pbs_tx(u32 dev_num);
40 
41 #endif /* _DDR3_TRAINING_IP_PBS_H_ */
42