1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR3_TRAINING_IP_FLOW_H_ 8 #define _DDR3_TRAINING_IP_FLOW_H_ 9 10 #include "ddr3_training_ip.h" 11 #include "ddr3_training_ip_pbs.h" 12 13 #define MRS0_CMD 0x3 14 #define MRS1_CMD 0x4 15 #define MRS2_CMD 0x8 16 #define MRS3_CMD 0x9 17 18 /* 19 * Definitions of INTERFACE registers 20 */ 21 22 #define READ_BUFFER_SELECT 0x14a4 23 24 /* 25 * Definitions of PHY registers 26 */ 27 28 #define KILLER_PATTERN_LENGTH 32 29 #define EXT_ACCESS_BURST_LENGTH 8 30 31 #define IS_ACTIVE(if_mask , if_id) \ 32 ((if_mask) & (1 << (if_id))) 33 #define VALIDATE_ACTIVE(mask, id) \ 34 { \ 35 if (IS_ACTIVE(mask, id) == 0) \ 36 continue; \ 37 } 38 39 #define GET_TOPOLOGY_NUM_OF_BUSES() \ 40 (ddr3_get_topology_map()->num_of_bus_per_interface) 41 42 #define DDR3_IS_ECC_PUP3_MODE(if_mask) \ 43 (((if_mask) == 0xb) ? 1 : 0) 44 #define DDR3_IS_ECC_PUP4_MODE(if_mask) \ 45 (((((if_mask) & 0x10) == 0)) ? 0 : 1) 46 #define DDR3_IS_16BIT_DRAM_MODE(mask) \ 47 (((((mask) & 0x4) == 0)) ? 1 : 0) 48 49 #define MEGA 1000000 50 #define BUS_WIDTH_IN_BITS 8 51 52 /* 53 * DFX address Space 54 * Table 2: DFX address space 55 * Address Bits Value Description 56 * [31 : 20] 0x? DFX base address bases PCIe mapping 57 * [19 : 15] 0...Number_of_client-1 Client Index inside pipe. 58 * See also Table 1 Multi_cast = 29 Broadcast = 28 59 * [14 : 13] 2'b01 Access to Client Internal Register 60 * [12 : 0] Client Internal Register offset See related Client Registers 61 * [14 : 13] 2'b00 Access to Ram Wrappers Internal Register 62 * [12 : 6] 0 Number_of_rams-1 Ram Index inside Client 63 * [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers 64 * Registers 65 */ 66 67 /* nsec */ 68 #define TREFI_LOW 7800 69 #define TREFI_HIGH 3900 70 71 #define TR2R_VALUE_REG 0x180 72 #define TR2R_MASK_REG 0x180 73 #define TRFC_MASK_REG 0x7f 74 #define TR2W_MASK_REG 0x600 75 #define TW2W_HIGH_VALUE_REG 0x1800 76 #define TW2W_HIGH_MASK_REG 0xf800 77 #define TRFC_HIGH_VALUE_REG 0x20000 78 #define TRFC_HIGH_MASK_REG 0x70000 79 #define TR2R_HIGH_VALUE_REG 0x0 80 #define TR2R_HIGH_MASK_REG 0x380000 81 #define TMOD_VALUE_REG 0x16000000 82 #define TMOD_MASK_REG 0x1e000000 83 #define T_VALUE_REG 0x40000000 84 #define T_MASK_REG 0xc0000000 85 #define AUTO_ZQC_TIMING 15384 86 #define WRITE_XBAR_PORT1 0xc03f8077 87 #define READ_XBAR_PORT1 0xc03f8073 88 #define DISABLE_DDR_TUNING_DATA 0x02294285 89 #define ENABLE_DDR_TUNING_DATA 0x12294285 90 91 #define ODPG_TRAINING_STATUS_REG 0x18488 92 #define ODPG_TRAINING_TRIGGER_REG 0x1030 93 #define ODPG_STATUS_DONE_REG 0x16fc 94 #define ODPG_ENABLE_REG 0x186d4 95 #define ODPG_ENABLE_OFFS 0 96 #define ODPG_DISABLE_OFFS 8 97 98 #define ODPG_TRAINING_CONTROL_REG 0x1034 99 #define ODPG_OBJ1_OPCODE_REG 0x103c 100 #define ODPG_OBJ1_ITER_CNT_REG 0x10b4 101 #define CALIB_OBJ_PRFA_REG 0x10c4 102 #define ODPG_WRITE_LEVELING_DONE_CNTR_REG 0x10f8 103 #define ODPG_WRITE_READ_MODE_ENABLE_REG 0x10fc 104 #define TRAINING_OPCODE_1_REG 0x10b4 105 #define SDRAM_CONFIGURATION_REG 0x1400 106 #define DDR_CONTROL_LOW_REG 0x1404 107 #define SDRAM_TIMING_LOW_REG 0x1408 108 #define SDRAM_TIMING_HIGH_REG 0x140c 109 #define SDRAM_ACCESS_CONTROL_REG 0x1410 110 #define SDRAM_OPEN_PAGE_CONTROL_REG 0x1414 111 #define SDRAM_OPERATION_REG 0x1418 112 #define DUNIT_CONTROL_HIGH_REG 0x1424 113 #define ODT_TIMING_LOW 0x1428 114 #define DDR_TIMING_REG 0x142c 115 #define ODT_TIMING_HI_REG 0x147c 116 #define SDRAM_INIT_CONTROL_REG 0x1480 117 #define SDRAM_ODT_CONTROL_HIGH_REG 0x1498 118 #define DUNIT_ODT_CONTROL_REG 0x149c 119 #define READ_BUFFER_SELECT_REG 0x14a4 120 #define DUNIT_MMASK_REG 0x14b0 121 #define CALIB_MACHINE_CTRL_REG 0x14cc 122 #define DRAM_DLL_TIMING_REG 0x14e0 123 #define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4 124 #define DRAM_ZQ_TIMING_REG 0x14e8 125 #define DFS_REG 0x1528 126 #define READ_DATA_SAMPLE_DELAY 0x1538 127 #define READ_DATA_READY_DELAY 0x153c 128 #define TRAINING_REG 0x15b0 129 #define TRAINING_SW_1_REG 0x15b4 130 #define TRAINING_SW_2_REG 0x15b8 131 #define TRAINING_PATTERN_BASE_ADDRESS_REG 0x15bc 132 #define TRAINING_DBG_1_REG 0x15c0 133 #define TRAINING_DBG_2_REG 0x15c4 134 #define TRAINING_DBG_3_REG 0x15c8 135 #define RANK_CTRL_REG 0x15e0 136 #define TIMING_REG 0x15e4 137 #define DRAM_PHY_CONFIGURATION 0x15ec 138 #define MR0_REG 0x15d0 139 #define MR1_REG 0x15d4 140 #define MR2_REG 0x15d8 141 #define MR3_REG 0x15dc 142 #define TIMING_REG 0x15e4 143 #define ODPG_CTRL_CONTROL_REG 0x1600 144 #define ODPG_DATA_CONTROL_REG 0x1630 145 #define ODPG_PATTERN_ADDR_OFFSET_REG 0x1638 146 #define ODPG_DATA_BUF_SIZE_REG 0x163c 147 #define PHY_LOCK_STATUS_REG 0x1674 148 #define PHY_REG_FILE_ACCESS 0x16a0 149 #define TRAINING_WRITE_LEVELING_REG 0x16ac 150 #define ODPG_PATTERN_ADDR_REG 0x16b0 151 #define ODPG_PATTERN_DATA_HI_REG 0x16b4 152 #define ODPG_PATTERN_DATA_LOW_REG 0x16b8 153 #define ODPG_BIST_LAST_FAIL_ADDR_REG 0x16bc 154 #define ODPG_BIST_DATA_ERROR_COUNTER_REG 0x16c0 155 #define ODPG_BIST_FAILED_DATA_HI_REG 0x16c4 156 #define ODPG_BIST_FAILED_DATA_LOW_REG 0x16c8 157 #define ODPG_WRITE_DATA_ERROR_REG 0x16cc 158 #define CS_ENABLE_REG 0x16d8 159 #define WR_LEVELING_DQS_PATTERN_REG 0x16dc 160 161 #define ODPG_BIST_DONE 0x186d4 162 #define ODPG_BIST_DONE_BIT_OFFS 0 163 #define ODPG_BIST_DONE_BIT_VALUE 0 164 165 #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 166 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 167 #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838 168 #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c 169 #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0 170 171 #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4 172 #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8 173 #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc 174 #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0 175 #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4 176 #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8 177 #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc 178 #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0 179 #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4 180 #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8 181 #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc 182 #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930 183 #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934 184 #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938 185 #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c 186 #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0 187 #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4 188 #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8 189 #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc 190 #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0 191 #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4 192 #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8 193 #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc 194 #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0 195 #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4 196 #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8 197 #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc 198 #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30 199 #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34 200 #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38 201 #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c 202 #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0 203 #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4 204 #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8 205 #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc 206 #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0 207 #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4 208 #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8 209 #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc 210 #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0 211 212 #define WL_PHY_REG 0x0 213 #define WRITE_CENTRALIZATION_PHY_REG 0x1 214 #define RL_PHY_REG 0x2 215 #define READ_CENTRALIZATION_PHY_REG 0x3 216 #define PBS_RX_PHY_REG 0x50 217 #define PBS_TX_PHY_REG 0x10 218 #define PHY_CONTROL_PHY_REG 0x90 219 #define BW_PHY_REG 0x92 220 #define RATE_PHY_REG 0x94 221 #define CMOS_CONFIG_PHY_REG 0xa2 222 #define PAD_ZRI_CALIB_PHY_REG 0xa4 223 #define PAD_ODT_CALIB_PHY_REG 0xa6 224 #define PAD_CONFIG_PHY_REG 0xa8 225 #define PAD_PRE_DISABLE_PHY_REG 0xa9 226 #define TEST_ADLL_REG 0xbf 227 #define CSN_IOB_VREF_REG(cs) (0xdb + (cs * 12)) 228 #define CSN_IO_BASE_VREF_REG(cs) (0xd0 + (cs * 12)) 229 230 #define RESULT_DB_PHY_REG_ADDR 0xc0 231 #define RESULT_DB_PHY_REG_RX_OFFSET 5 232 #define RESULT_DB_PHY_REG_TX_OFFSET 0 233 234 /* TBD - for NP5 use only CS 0 */ 235 #define PHY_WRITE_DELAY(cs) WL_PHY_REG 236 /*( ( _cs_ == 0 ) ? 0x0 : 0x4 )*/ 237 /* TBD - for NP5 use only CS 0 */ 238 #define PHY_READ_DELAY(cs) RL_PHY_REG 239 240 #define DDR0_ADDR_1 0xf8258 241 #define DDR0_ADDR_2 0xf8254 242 #define DDR1_ADDR_1 0xf8270 243 #define DDR1_ADDR_2 0xf8270 244 #define DDR2_ADDR_1 0xf825c 245 #define DDR2_ADDR_2 0xf825c 246 #define DDR3_ADDR_1 0xf8264 247 #define DDR3_ADDR_2 0xf8260 248 #define DDR4_ADDR_1 0xf8274 249 #define DDR4_ADDR_2 0xf8274 250 251 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 252 253 #define GET_BLOCK_ID_MAX_FREQ(dev_num, block_id) 800000 254 #define CS0_RD_LVL_REF_DLY_OFFS 0 255 #define CS0_RD_LVL_REF_DLY_LEN 0 256 #define CS0_RD_LVL_PH_SEL_OFFS 0 257 #define CS0_RD_LVL_PH_SEL_LEN 0 258 259 #define CS_REGISTER_ADDR_OFFSET 4 260 #define CALIBRATED_OBJECTS_REG_ADDR_OFFSET 0x10 261 262 #define MAX_POLLING_ITERATIONS 100000 263 264 #define PHASE_REG_OFFSET 32 265 #define NUM_BYTES_IN_BURST 31 266 #define NUM_OF_CS 4 267 #define CS_REG_VALUE(cs_num) (cs_mask_reg[cs_num]) 268 #define ADLL_LENGTH 32 269 270 struct write_supp_result { 271 enum hws_wl_supp stage; 272 int is_pup_fail; 273 }; 274 275 struct page_element { 276 enum hws_page_size page_size_8bit; 277 /* page size in 8 bits bus width */ 278 enum hws_page_size page_size_16bit; 279 /* page size in 16 bits bus width */ 280 u32 ui_page_mask; 281 /* Mask used in register */ 282 }; 283 284 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 285 enum hws_ddr_freq frequency, 286 u32 *round_trip_delay_arr); 287 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 288 enum hws_ddr_freq frequency, 289 u32 *total_round_trip_delay_arr); 290 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, 291 u32 if_id, u32 reg_addr, u32 data_value, u32 mask); 292 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, 293 u32 if_id, u32 exp_value, u32 mask, u32 offset, 294 u32 poll_tries); 295 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, 296 u32 if_id, u32 reg_addr, u32 *data, u32 mask); 297 int ddr3_tip_bus_read_modify_write(u32 dev_num, 298 enum hws_access_type access_type, 299 u32 if_id, u32 phy_id, 300 enum hws_ddr_phy phy_type, 301 u32 reg_addr, u32 data_value, u32 reg_mask); 302 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 303 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, 304 u32 *data); 305 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, 306 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id, 307 enum hws_ddr_phy e_phy_type, u32 reg_addr, 308 u32 data_value); 309 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 310 enum hws_ddr_freq memory_freq); 311 int ddr3_tip_adjust_dqs(u32 dev_num); 312 int ddr3_tip_init_controller(u32 dev_num); 313 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, 314 u32 num_of_bursts, u32 *addr); 315 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, 316 u32 num_of_bursts, u32 *addr); 317 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq); 318 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num); 319 int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq); 320 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num); 321 int ddr3_tip_dynamic_write_leveling(u32 dev_num); 322 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num); 323 int ddr3_tip_static_init_controller(u32 dev_num); 324 int ddr3_tip_configure_phy(u32 dev_num); 325 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, 326 u32 if_id, enum hws_pattern pattern, 327 u32 load_addr); 328 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern); 329 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, 330 u32 if_id, enum hws_dir direction, u32 tx_phases, 331 u32 tx_burst_size, u32 rx_phases, 332 u32 delay_between_burst, u32 rd_mode, u32 cs_num, 333 u32 addr_stress_jump, u32 single_pattern); 334 int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value); 335 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd, u32 data, 336 u32 mask); 337 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset); 338 int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id); 339 int ddr3_tip_reset_fifo_ptr(u32 dev_num); 340 int read_pup_value(int pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 341 int reg_addr, u32 mask); 342 int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 343 int reg_addr, u32 mask); 344 int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 345 int reg_addr); 346 int ddr3_tip_tune_training_params(u32 dev_num, 347 struct tune_train_params *params); 348 349 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */ 350