1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_FLOW_H_ 7 #define _DDR3_TRAINING_IP_FLOW_H_ 8 9 #include "ddr3_training_ip.h" 10 #include "ddr3_training_ip_pbs.h" 11 12 #define MRS0_CMD 0x3 13 #define MRS1_CMD 0x4 14 #define MRS2_CMD 0x8 15 #define MRS3_CMD 0x9 16 17 /* 18 * Definitions of INTERFACE registers 19 */ 20 21 #define READ_BUFFER_SELECT 0x14a4 22 23 /* 24 * Definitions of PHY registers 25 */ 26 27 #define KILLER_PATTERN_LENGTH 32 28 #define EXT_ACCESS_BURST_LENGTH 8 29 30 #define IS_ACTIVE(if_mask , if_id) \ 31 ((if_mask) & (1 << (if_id))) 32 #define VALIDATE_ACTIVE(mask, id) \ 33 { \ 34 if (IS_ACTIVE(mask, id) == 0) \ 35 continue; \ 36 } 37 38 #define GET_TOPOLOGY_NUM_OF_BUSES() \ 39 (ddr3_get_topology_map()->num_of_bus_per_interface) 40 41 #define DDR3_IS_ECC_PUP3_MODE(if_mask) \ 42 (((if_mask) == 0xb) ? 1 : 0) 43 #define DDR3_IS_ECC_PUP4_MODE(if_mask) \ 44 (((((if_mask) & 0x10) == 0)) ? 0 : 1) 45 #define DDR3_IS_16BIT_DRAM_MODE(mask) \ 46 (((((mask) & 0x4) == 0)) ? 1 : 0) 47 48 #define MEGA 1000000 49 #define BUS_WIDTH_IN_BITS 8 50 51 /* 52 * DFX address Space 53 * Table 2: DFX address space 54 * Address Bits Value Description 55 * [31 : 20] 0x? DFX base address bases PCIe mapping 56 * [19 : 15] 0...Number_of_client-1 Client Index inside pipe. 57 * See also Table 1 Multi_cast = 29 Broadcast = 28 58 * [14 : 13] 2'b01 Access to Client Internal Register 59 * [12 : 0] Client Internal Register offset See related Client Registers 60 * [14 : 13] 2'b00 Access to Ram Wrappers Internal Register 61 * [12 : 6] 0 Number_of_rams-1 Ram Index inside Client 62 * [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers 63 * Registers 64 */ 65 66 /* nsec */ 67 #define TREFI_LOW 7800 68 #define TREFI_HIGH 3900 69 70 #define TR2R_VALUE_REG 0x180 71 #define TR2R_MASK_REG 0x180 72 #define TRFC_MASK_REG 0x7f 73 #define TR2W_MASK_REG 0x600 74 #define TW2W_HIGH_VALUE_REG 0x1800 75 #define TW2W_HIGH_MASK_REG 0xf800 76 #define TRFC_HIGH_VALUE_REG 0x20000 77 #define TRFC_HIGH_MASK_REG 0x70000 78 #define TR2R_HIGH_VALUE_REG 0x0 79 #define TR2R_HIGH_MASK_REG 0x380000 80 #define TMOD_VALUE_REG 0x16000000 81 #define TMOD_MASK_REG 0x1e000000 82 #define T_VALUE_REG 0x40000000 83 #define T_MASK_REG 0xc0000000 84 #define AUTO_ZQC_TIMING 15384 85 #define WRITE_XBAR_PORT1 0xc03f8077 86 #define READ_XBAR_PORT1 0xc03f8073 87 #define DISABLE_DDR_TUNING_DATA 0x02294285 88 #define ENABLE_DDR_TUNING_DATA 0x12294285 89 90 #define ODPG_TRAINING_STATUS_REG 0x18488 91 #define ODPG_TRAINING_TRIGGER_REG 0x1030 92 #define ODPG_STATUS_DONE_REG 0x16fc 93 #define ODPG_ENABLE_REG 0x186d4 94 #define ODPG_ENABLE_OFFS 0 95 #define ODPG_DISABLE_OFFS 8 96 97 #define ODPG_TRAINING_CONTROL_REG 0x1034 98 #define ODPG_OBJ1_OPCODE_REG 0x103c 99 #define ODPG_OBJ1_ITER_CNT_REG 0x10b4 100 #define CALIB_OBJ_PRFA_REG 0x10c4 101 #define ODPG_WRITE_LEVELING_DONE_CNTR_REG 0x10f8 102 #define ODPG_WRITE_READ_MODE_ENABLE_REG 0x10fc 103 #define TRAINING_OPCODE_1_REG 0x10b4 104 #define SDRAM_CONFIGURATION_REG 0x1400 105 #define DDR_CONTROL_LOW_REG 0x1404 106 #define SDRAM_TIMING_LOW_REG 0x1408 107 #define SDRAM_TIMING_HIGH_REG 0x140c 108 #define SDRAM_ACCESS_CONTROL_REG 0x1410 109 #define SDRAM_OPEN_PAGE_CONTROL_REG 0x1414 110 #define SDRAM_OPERATION_REG 0x1418 111 #define DUNIT_CONTROL_HIGH_REG 0x1424 112 #define ODT_TIMING_LOW 0x1428 113 #define DDR_TIMING_REG 0x142c 114 #define ODT_TIMING_HI_REG 0x147c 115 #define SDRAM_INIT_CONTROL_REG 0x1480 116 #define SDRAM_ODT_CONTROL_HIGH_REG 0x1498 117 #define DUNIT_ODT_CONTROL_REG 0x149c 118 #define READ_BUFFER_SELECT_REG 0x14a4 119 #define DUNIT_MMASK_REG 0x14b0 120 #define CALIB_MACHINE_CTRL_REG 0x14cc 121 #define DRAM_DLL_TIMING_REG 0x14e0 122 #define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4 123 #define DRAM_ZQ_TIMING_REG 0x14e8 124 #define DFS_REG 0x1528 125 #define READ_DATA_SAMPLE_DELAY 0x1538 126 #define READ_DATA_READY_DELAY 0x153c 127 #define TRAINING_REG 0x15b0 128 #define TRAINING_SW_1_REG 0x15b4 129 #define TRAINING_SW_2_REG 0x15b8 130 #define TRAINING_PATTERN_BASE_ADDRESS_REG 0x15bc 131 #define TRAINING_DBG_1_REG 0x15c0 132 #define TRAINING_DBG_2_REG 0x15c4 133 #define TRAINING_DBG_3_REG 0x15c8 134 #define RANK_CTRL_REG 0x15e0 135 #define TIMING_REG 0x15e4 136 #define DRAM_PHY_CONFIGURATION 0x15ec 137 #define MR0_REG 0x15d0 138 #define MR1_REG 0x15d4 139 #define MR2_REG 0x15d8 140 #define MR3_REG 0x15dc 141 #define TIMING_REG 0x15e4 142 #define ODPG_CTRL_CONTROL_REG 0x1600 143 #define ODPG_DATA_CONTROL_REG 0x1630 144 #define ODPG_PATTERN_ADDR_OFFSET_REG 0x1638 145 #define ODPG_DATA_BUF_SIZE_REG 0x163c 146 #define PHY_LOCK_STATUS_REG 0x1674 147 #define PHY_REG_FILE_ACCESS 0x16a0 148 #define TRAINING_WRITE_LEVELING_REG 0x16ac 149 #define ODPG_PATTERN_ADDR_REG 0x16b0 150 #define ODPG_PATTERN_DATA_HI_REG 0x16b4 151 #define ODPG_PATTERN_DATA_LOW_REG 0x16b8 152 #define ODPG_BIST_LAST_FAIL_ADDR_REG 0x16bc 153 #define ODPG_BIST_DATA_ERROR_COUNTER_REG 0x16c0 154 #define ODPG_BIST_FAILED_DATA_HI_REG 0x16c4 155 #define ODPG_BIST_FAILED_DATA_LOW_REG 0x16c8 156 #define ODPG_WRITE_DATA_ERROR_REG 0x16cc 157 #define CS_ENABLE_REG 0x16d8 158 #define WR_LEVELING_DQS_PATTERN_REG 0x16dc 159 160 #define ODPG_BIST_DONE 0x186d4 161 #define ODPG_BIST_DONE_BIT_OFFS 0 162 #define ODPG_BIST_DONE_BIT_VALUE 0 163 164 #define RESULT_CONTROL_BYTE_PUP_0_REG 0x1830 165 #define RESULT_CONTROL_BYTE_PUP_1_REG 0x1834 166 #define RESULT_CONTROL_BYTE_PUP_2_REG 0x1838 167 #define RESULT_CONTROL_BYTE_PUP_3_REG 0x183c 168 #define RESULT_CONTROL_BYTE_PUP_4_REG 0x18b0 169 170 #define RESULT_CONTROL_PUP_0_BIT_0_REG 0x18b4 171 #define RESULT_CONTROL_PUP_0_BIT_1_REG 0x18b8 172 #define RESULT_CONTROL_PUP_0_BIT_2_REG 0x18bc 173 #define RESULT_CONTROL_PUP_0_BIT_3_REG 0x18c0 174 #define RESULT_CONTROL_PUP_0_BIT_4_REG 0x18c4 175 #define RESULT_CONTROL_PUP_0_BIT_5_REG 0x18c8 176 #define RESULT_CONTROL_PUP_0_BIT_6_REG 0x18cc 177 #define RESULT_CONTROL_PUP_0_BIT_7_REG 0x18f0 178 #define RESULT_CONTROL_PUP_1_BIT_0_REG 0x18f4 179 #define RESULT_CONTROL_PUP_1_BIT_1_REG 0x18f8 180 #define RESULT_CONTROL_PUP_1_BIT_2_REG 0x18fc 181 #define RESULT_CONTROL_PUP_1_BIT_3_REG 0x1930 182 #define RESULT_CONTROL_PUP_1_BIT_4_REG 0x1934 183 #define RESULT_CONTROL_PUP_1_BIT_5_REG 0x1938 184 #define RESULT_CONTROL_PUP_1_BIT_6_REG 0x193c 185 #define RESULT_CONTROL_PUP_1_BIT_7_REG 0x19b0 186 #define RESULT_CONTROL_PUP_2_BIT_0_REG 0x19b4 187 #define RESULT_CONTROL_PUP_2_BIT_1_REG 0x19b8 188 #define RESULT_CONTROL_PUP_2_BIT_2_REG 0x19bc 189 #define RESULT_CONTROL_PUP_2_BIT_3_REG 0x19c0 190 #define RESULT_CONTROL_PUP_2_BIT_4_REG 0x19c4 191 #define RESULT_CONTROL_PUP_2_BIT_5_REG 0x19c8 192 #define RESULT_CONTROL_PUP_2_BIT_6_REG 0x19cc 193 #define RESULT_CONTROL_PUP_2_BIT_7_REG 0x19f0 194 #define RESULT_CONTROL_PUP_3_BIT_0_REG 0x19f4 195 #define RESULT_CONTROL_PUP_3_BIT_1_REG 0x19f8 196 #define RESULT_CONTROL_PUP_3_BIT_2_REG 0x19fc 197 #define RESULT_CONTROL_PUP_3_BIT_3_REG 0x1a30 198 #define RESULT_CONTROL_PUP_3_BIT_4_REG 0x1a34 199 #define RESULT_CONTROL_PUP_3_BIT_5_REG 0x1a38 200 #define RESULT_CONTROL_PUP_3_BIT_6_REG 0x1a3c 201 #define RESULT_CONTROL_PUP_3_BIT_7_REG 0x1ab0 202 #define RESULT_CONTROL_PUP_4_BIT_0_REG 0x1ab4 203 #define RESULT_CONTROL_PUP_4_BIT_1_REG 0x1ab8 204 #define RESULT_CONTROL_PUP_4_BIT_2_REG 0x1abc 205 #define RESULT_CONTROL_PUP_4_BIT_3_REG 0x1ac0 206 #define RESULT_CONTROL_PUP_4_BIT_4_REG 0x1ac4 207 #define RESULT_CONTROL_PUP_4_BIT_5_REG 0x1ac8 208 #define RESULT_CONTROL_PUP_4_BIT_6_REG 0x1acc 209 #define RESULT_CONTROL_PUP_4_BIT_7_REG 0x1af0 210 211 #define WL_PHY_REG 0x0 212 #define WRITE_CENTRALIZATION_PHY_REG 0x1 213 #define RL_PHY_REG 0x2 214 #define READ_CENTRALIZATION_PHY_REG 0x3 215 #define PBS_RX_PHY_REG 0x50 216 #define PBS_TX_PHY_REG 0x10 217 #define PHY_CONTROL_PHY_REG 0x90 218 #define BW_PHY_REG 0x92 219 #define RATE_PHY_REG 0x94 220 #define CMOS_CONFIG_PHY_REG 0xa2 221 #define PAD_ZRI_CALIB_PHY_REG 0xa4 222 #define PAD_ODT_CALIB_PHY_REG 0xa6 223 #define PAD_CONFIG_PHY_REG 0xa8 224 #define PAD_PRE_DISABLE_PHY_REG 0xa9 225 #define TEST_ADLL_REG 0xbf 226 #define CSN_IOB_VREF_REG(cs) (0xdb + (cs * 12)) 227 #define CSN_IO_BASE_VREF_REG(cs) (0xd0 + (cs * 12)) 228 229 #define RESULT_DB_PHY_REG_ADDR 0xc0 230 #define RESULT_DB_PHY_REG_RX_OFFSET 5 231 #define RESULT_DB_PHY_REG_TX_OFFSET 0 232 233 /* TBD - for NP5 use only CS 0 */ 234 #define PHY_WRITE_DELAY(cs) WL_PHY_REG 235 /*( ( _cs_ == 0 ) ? 0x0 : 0x4 )*/ 236 /* TBD - for NP5 use only CS 0 */ 237 #define PHY_READ_DELAY(cs) RL_PHY_REG 238 239 #define DDR0_ADDR_1 0xf8258 240 #define DDR0_ADDR_2 0xf8254 241 #define DDR1_ADDR_1 0xf8270 242 #define DDR1_ADDR_2 0xf8270 243 #define DDR2_ADDR_1 0xf825c 244 #define DDR2_ADDR_2 0xf825c 245 #define DDR3_ADDR_1 0xf8264 246 #define DDR3_ADDR_2 0xf8260 247 #define DDR4_ADDR_1 0xf8274 248 #define DDR4_ADDR_2 0xf8274 249 250 #define GENERAL_PURPOSE_RESERVED0_REG 0x182e0 251 252 #define GET_BLOCK_ID_MAX_FREQ(dev_num, block_id) 800000 253 #define CS0_RD_LVL_REF_DLY_OFFS 0 254 #define CS0_RD_LVL_REF_DLY_LEN 0 255 #define CS0_RD_LVL_PH_SEL_OFFS 0 256 #define CS0_RD_LVL_PH_SEL_LEN 0 257 258 #define CS_REGISTER_ADDR_OFFSET 4 259 #define CALIBRATED_OBJECTS_REG_ADDR_OFFSET 0x10 260 261 #define MAX_POLLING_ITERATIONS 100000 262 263 #define PHASE_REG_OFFSET 32 264 #define NUM_BYTES_IN_BURST 31 265 #define NUM_OF_CS 4 266 #define CS_REG_VALUE(cs_num) (cs_mask_reg[cs_num]) 267 #define ADLL_LENGTH 32 268 269 struct write_supp_result { 270 enum hws_wl_supp stage; 271 int is_pup_fail; 272 }; 273 274 struct page_element { 275 enum hws_page_size page_size_8bit; 276 /* page size in 8 bits bus width */ 277 enum hws_page_size page_size_16bit; 278 /* page size in 16 bits bus width */ 279 u32 ui_page_mask; 280 /* Mask used in register */ 281 }; 282 283 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 284 enum hws_ddr_freq frequency, 285 u32 *round_trip_delay_arr); 286 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 287 enum hws_ddr_freq frequency, 288 u32 *total_round_trip_delay_arr); 289 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, 290 u32 if_id, u32 reg_addr, u32 data_value, u32 mask); 291 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, 292 u32 if_id, u32 exp_value, u32 mask, u32 offset, 293 u32 poll_tries); 294 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, 295 u32 if_id, u32 reg_addr, u32 *data, u32 mask); 296 int ddr3_tip_bus_read_modify_write(u32 dev_num, 297 enum hws_access_type access_type, 298 u32 if_id, u32 phy_id, 299 enum hws_ddr_phy phy_type, 300 u32 reg_addr, u32 data_value, u32 reg_mask); 301 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 302 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, 303 u32 *data); 304 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, 305 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id, 306 enum hws_ddr_phy e_phy_type, u32 reg_addr, 307 u32 data_value); 308 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 309 enum hws_ddr_freq memory_freq); 310 int ddr3_tip_adjust_dqs(u32 dev_num); 311 int ddr3_tip_init_controller(u32 dev_num); 312 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, 313 u32 num_of_bursts, u32 *addr); 314 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, 315 u32 num_of_bursts, u32 *addr); 316 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq); 317 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num); 318 int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq); 319 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num); 320 int ddr3_tip_dynamic_write_leveling(u32 dev_num); 321 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num); 322 int ddr3_tip_static_init_controller(u32 dev_num); 323 int ddr3_tip_configure_phy(u32 dev_num); 324 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type, 325 u32 if_id, enum hws_pattern pattern, 326 u32 load_addr); 327 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern); 328 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, 329 u32 if_id, enum hws_dir direction, u32 tx_phases, 330 u32 tx_burst_size, u32 rx_phases, 331 u32 delay_between_burst, u32 rd_mode, u32 cs_num, 332 u32 addr_stress_jump, u32 single_pattern); 333 int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value); 334 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, u32 cmd, u32 data, 335 u32 mask); 336 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset); 337 int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask, u32 *if_id); 338 int ddr3_tip_reset_fifo_ptr(u32 dev_num); 339 int read_pup_value(int pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 340 int reg_addr, u32 mask); 341 int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 342 int reg_addr, u32 mask); 343 int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 344 int reg_addr); 345 int ddr3_tip_tune_training_params(u32 dev_num, 346 struct tune_train_params *params); 347 348 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */ 349