1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR3_TRAINING_IP_DEF_H 8 #define _DDR3_TRAINING_IP_DEF_H 9 10 #include "silicon_if.h" 11 12 #define PATTERN_55 0x55555555 13 #define PATTERN_AA 0xaaaaaaaa 14 #define PATTERN_80 0x80808080 15 #define PATTERN_20 0x20202020 16 #define PATTERN_01 0x01010101 17 #define PATTERN_FF 0xffffffff 18 #define PATTERN_00 0x00000000 19 20 /* 16bit bus width patterns */ 21 #define PATTERN_55AA 0x5555aaaa 22 #define PATTERN_00FF 0x0000ffff 23 #define PATTERN_0080 0x00008080 24 25 #define INVALID_VALUE 0xffffffff 26 #define MAX_NUM_OF_DUNITS 32 27 /* 28 * length *2 = length in words of pattern, first low address, 29 * second high address 30 */ 31 #define TEST_PATTERN_LENGTH 4 32 #define KILLER_PATTERN_DQ_NUMBER 8 33 #define SSO_DQ_NUMBER 4 34 #define PATTERN_MAXIMUM_LENGTH 64 35 #define ADLL_TX_LENGTH 64 36 #define ADLL_RX_LENGTH 32 37 38 #define PARAM_NOT_CARE 0 39 40 #define READ_LEVELING_PHY_OFFSET 2 41 #define WRITE_LEVELING_PHY_OFFSET 0 42 43 #define MASK_ALL_BITS 0xffffffff 44 45 #define CS_BIT_MASK 0xf 46 47 /* DFX access */ 48 #define BROADCAST_ID 28 49 #define MULTICAST_ID 29 50 51 #define XSB_BASE_ADDR 0x00004000 52 #define XSB_CTRL_0_REG 0x00000000 53 #define XSB_CTRL_1_REG 0x00000004 54 #define XSB_CMD_REG 0x00000008 55 #define XSB_ADDRESS_REG 0x0000000c 56 #define XSB_DATA_REG 0x00000010 57 #define PIPE_ENABLE_ADDR 0x000f8000 58 #define ENABLE_DDR_TUNING_ADDR 0x000f829c 59 60 #define CLIENT_BASE_ADDR 0x00002000 61 #define CLIENT_CTRL_REG 0x00000000 62 63 #define TARGET_INT 0x1801 64 #define TARGET_EXT 0x180e 65 #define BYTE_EN 0 66 #define CMD_READ 0 67 #define CMD_WRITE 1 68 69 #define INTERNAL_ACCESS_PORT 1 70 #define EXECUTING 1 71 #define ACCESS_EXT 1 72 #define CS2_EXIST_BIT 2 73 #define TRAINING_ID 0xf 74 #define EXT_TRAINING_ID 1 75 #define EXT_MODE 0x4 76 77 #define GET_RESULT_STATE(res) (res) 78 #define SET_RESULT_STATE(res, state) (res = state) 79 80 #define _1K 0x00000400 81 #define _4K 0x00001000 82 #define _8K 0x00002000 83 #define _16K 0x00004000 84 #define _32K 0x00008000 85 #define _64K 0x00010000 86 #define _128K 0x00020000 87 #define _256K 0x00040000 88 #define _512K 0x00080000 89 90 #define _1M 0x00100000 91 #define _2M 0x00200000 92 #define _4M 0x00400000 93 #define _8M 0x00800000 94 #define _16M 0x01000000 95 #define _32M 0x02000000 96 #define _64M 0x04000000 97 #define _128M 0x08000000 98 #define _256M 0x10000000 99 #define _512M 0x20000000 100 101 #define _1G 0x40000000 102 #define _2G 0x80000000 103 104 #define ADDR_SIZE_512MB 0x04000000 105 #define ADDR_SIZE_1GB 0x08000000 106 #define ADDR_SIZE_2GB 0x10000000 107 #define ADDR_SIZE_4GB 0x20000000 108 #define ADDR_SIZE_8GB 0x40000000 109 110 enum hws_edge_compare { 111 EDGE_PF, 112 EDGE_FP, 113 EDGE_FPF, 114 EDGE_PFP 115 }; 116 117 enum hws_control_element { 118 HWS_CONTROL_ELEMENT_ADLL, /* per bit 1 edge */ 119 HWS_CONTROL_ELEMENT_DQ_SKEW, 120 HWS_CONTROL_ELEMENT_DQS_SKEW 121 }; 122 123 enum hws_search_dir { 124 HWS_LOW2HIGH, 125 HWS_HIGH2LOW, 126 HWS_SEARCH_DIR_LIMIT 127 }; 128 129 enum hws_page_size { 130 PAGE_SIZE_1K, 131 PAGE_SIZE_2K 132 }; 133 134 enum hws_operation { 135 OPERATION_READ = 0, 136 OPERATION_WRITE = 1 137 }; 138 139 enum hws_training_ip_stat { 140 HWS_TRAINING_IP_STATUS_FAIL, 141 HWS_TRAINING_IP_STATUS_SUCCESS, 142 HWS_TRAINING_IP_STATUS_TIMEOUT 143 }; 144 145 enum hws_ddr_cs { 146 CS_SINGLE, 147 CS_NON_SINGLE 148 }; 149 150 enum hws_ddr_phy { 151 DDR_PHY_DATA = 0, 152 DDR_PHY_CONTROL = 1 153 }; 154 155 enum hws_dir { 156 OPER_WRITE, 157 OPER_READ, 158 OPER_WRITE_AND_READ 159 }; 160 161 enum hws_wl_supp { 162 PHASE_SHIFT, 163 CLOCK_SHIFT, 164 ALIGN_SHIFT 165 }; 166 167 struct reg_data { 168 u32 reg_addr; 169 u32 reg_data; 170 u32 reg_mask; 171 }; 172 173 #endif /* _DDR3_TRAINING_IP_DEF_H */ 174