183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_DB_H_ 7f1df9364SStefan Roese #define _DDR3_TRAINING_IP_DB_H_ 8f1df9364SStefan Roese 9f1df9364SStefan Roese enum hws_pattern { 10f1df9364SStefan Roese PATTERN_PBS1, 11f1df9364SStefan Roese PATTERN_PBS2, 12*2b4ffbf6SChris Packham PATTERN_PBS3, 13*2b4ffbf6SChris Packham PATTERN_TEST, 14f1df9364SStefan Roese PATTERN_RL, 15*2b4ffbf6SChris Packham PATTERN_RL2, 16f1df9364SStefan Roese PATTERN_STATIC_PBS, 17f1df9364SStefan Roese PATTERN_KILLER_DQ0, 18f1df9364SStefan Roese PATTERN_KILLER_DQ1, 19f1df9364SStefan Roese PATTERN_KILLER_DQ2, 20f1df9364SStefan Roese PATTERN_KILLER_DQ3, 21f1df9364SStefan Roese PATTERN_KILLER_DQ4, 22f1df9364SStefan Roese PATTERN_KILLER_DQ5, 23f1df9364SStefan Roese PATTERN_KILLER_DQ6, 24f1df9364SStefan Roese PATTERN_KILLER_DQ7, 25*2b4ffbf6SChris Packham PATTERN_VREF, 26f1df9364SStefan Roese PATTERN_FULL_SSO0, 27f1df9364SStefan Roese PATTERN_FULL_SSO1, 28f1df9364SStefan Roese PATTERN_FULL_SSO2, 29f1df9364SStefan Roese PATTERN_FULL_SSO3, 30*2b4ffbf6SChris Packham PATTERN_LAST, 31*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ0, 32*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ1, 33*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ2, 34*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ3, 35*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ4, 36*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ5, 37*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ6, 38*2b4ffbf6SChris Packham PATTERN_SSO_FULL_XTALK_DQ7, 39*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ0, 40*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ1, 41*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ2, 42*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ3, 43*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ4, 44*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ5, 45*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ6, 46*2b4ffbf6SChris Packham PATTERN_SSO_XTALK_FREE_DQ7, 47*2b4ffbf6SChris Packham PATTERN_ISI_XTALK_FREE 48f1df9364SStefan Roese }; 49f1df9364SStefan Roese 50*2b4ffbf6SChris Packham enum mv_wl_supp_mode { 51*2b4ffbf6SChris Packham WRITE_LEVELING_SUPP_REG_MODE, 52*2b4ffbf6SChris Packham WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS, 53*2b4ffbf6SChris Packham WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4, 54*2b4ffbf6SChris Packham WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3, 55*2b4ffbf6SChris Packham WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8 56*2b4ffbf6SChris Packham }; 57*2b4ffbf6SChris Packham 58*2b4ffbf6SChris Packham enum mv_ddr_dev_attribute { 59*2b4ffbf6SChris Packham MV_ATTR_TIP_REV, 60*2b4ffbf6SChris Packham MV_ATTR_PHY_EDGE, 61*2b4ffbf6SChris Packham MV_ATTR_OCTET_PER_INTERFACE, 62*2b4ffbf6SChris Packham MV_ATTR_PLL_BEFORE_INIT, 63*2b4ffbf6SChris Packham MV_ATTR_TUNE_MASK, 64*2b4ffbf6SChris Packham MV_ATTR_INIT_FREQ, 65*2b4ffbf6SChris Packham MV_ATTR_MID_FREQ, 66*2b4ffbf6SChris Packham MV_ATTR_DFS_LOW_FREQ, 67*2b4ffbf6SChris Packham MV_ATTR_DFS_LOW_PHY, 68*2b4ffbf6SChris Packham MV_ATTR_DELAY_ENABLE, 69*2b4ffbf6SChris Packham MV_ATTR_CK_DELAY, 70*2b4ffbf6SChris Packham MV_ATTR_CA_DELAY, 71*2b4ffbf6SChris Packham MV_ATTR_INTERLEAVE_WA, 72*2b4ffbf6SChris Packham MV_ATTR_LAST 73*2b4ffbf6SChris Packham }; 74*2b4ffbf6SChris Packham 75*2b4ffbf6SChris Packham enum mv_ddr_tip_revison { 76*2b4ffbf6SChris Packham MV_TIP_REV_NA, 77*2b4ffbf6SChris Packham MV_TIP_REV_1, /* NP5 */ 78*2b4ffbf6SChris Packham MV_TIP_REV_2, /* BC2 */ 79*2b4ffbf6SChris Packham MV_TIP_REV_3, /* AC3 */ 80*2b4ffbf6SChris Packham MV_TIP_REV_4, /* A-380/A-390 */ 81*2b4ffbf6SChris Packham MV_TIP_REV_LAST 82*2b4ffbf6SChris Packham }; 83*2b4ffbf6SChris Packham 84*2b4ffbf6SChris Packham enum mv_ddr_phy_edge { 85*2b4ffbf6SChris Packham MV_DDR_PHY_EDGE_POSITIVE, 86*2b4ffbf6SChris Packham MV_DDR_PHY_EDGE_NEGATIVE 87*2b4ffbf6SChris Packham }; 88*2b4ffbf6SChris Packham 89*2b4ffbf6SChris Packham /* Device attribute functions */ 90*2b4ffbf6SChris Packham void ddr3_tip_dev_attr_init(u32 dev_num); 91*2b4ffbf6SChris Packham u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id); 92*2b4ffbf6SChris Packham void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value); 93*2b4ffbf6SChris Packham 94f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_DB_H_ */ 95