1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H 7f1df9364SStefan Roese #define _DDR3_TRAINING_IP_CENTRALIZATION_H 8f1df9364SStefan Roese 9f1df9364SStefan Roese int ddr3_tip_centralization_tx(u32 dev_num); 10f1df9364SStefan Roese int ddr3_tip_centralization_rx(u32 dev_num); 11f1df9364SStefan Roese int ddr3_tip_print_centralization_result(u32 dev_num); 12f1df9364SStefan Roese int ddr3_tip_special_rx(u32 dev_num); 13f1df9364SStefan Roese 14f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */ 15