1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_TRAINING_IP_H_ 7 #define _DDR3_TRAINING_IP_H_ 8 9 #include "ddr3_training_ip_def.h" 10 #include "ddr_topology_def.h" 11 #include "ddr_training_ip_db.h" 12 13 #define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29." 14 15 #define MAX_CS_NUM 4 16 #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM) 17 #define MAX_DQ_NUM 40 18 19 #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2) 20 #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1) 21 22 #define INIT_CONTROLLER_MASK_BIT 0x00000001 23 #define STATIC_LEVELING_MASK_BIT 0x00000002 24 #define SET_LOW_FREQ_MASK_BIT 0x00000004 25 #define LOAD_PATTERN_MASK_BIT 0x00000008 26 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010 27 #define WRITE_LEVELING_MASK_BIT 0x00000020 28 #define LOAD_PATTERN_2_MASK_BIT 0x00000040 29 #define READ_LEVELING_MASK_BIT 0x00000080 30 #define SW_READ_LEVELING_MASK_BIT 0x00000100 31 #define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200 32 #define PBS_RX_MASK_BIT 0x00000400 33 #define PBS_TX_MASK_BIT 0x00000800 34 #define SET_TARGET_FREQ_MASK_BIT 0x00001000 35 #define ADJUST_DQS_MASK_BIT 0x00002000 36 #define WRITE_LEVELING_TF_MASK_BIT 0x00004000 37 #define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000 38 #define READ_LEVELING_TF_MASK_BIT 0x00010000 39 #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000 40 #define DM_PBS_TX_MASK_BIT 0x00040000 41 #define CENTRALIZATION_RX_MASK_BIT 0x00100000 42 #define CENTRALIZATION_TX_MASK_BIT 0x00200000 43 #define TX_EMPHASIS_MASK_BIT 0x00400000 44 #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000 45 #define VREF_CALIBRATION_MASK_BIT 0x01000000 46 47 enum hws_result { 48 TEST_FAILED = 0, 49 TEST_SUCCESS = 1, 50 NO_TEST_DONE = 2 51 }; 52 53 enum hws_training_result { 54 RESULT_PER_BIT, 55 RESULT_PER_BYTE 56 }; 57 58 enum auto_tune_stage { 59 INIT_CONTROLLER, 60 STATIC_LEVELING, 61 SET_LOW_FREQ, 62 LOAD_PATTERN, 63 SET_MEDIUM_FREQ, 64 WRITE_LEVELING, 65 LOAD_PATTERN_2, 66 READ_LEVELING, 67 WRITE_LEVELING_SUPP, 68 PBS_RX, 69 PBS_TX, 70 SET_TARGET_FREQ, 71 ADJUST_DQS, 72 WRITE_LEVELING_TF, 73 READ_LEVELING_TF, 74 WRITE_LEVELING_SUPP_TF, 75 DM_PBS_TX, 76 VREF_CALIBRATION, 77 CENTRALIZATION_RX, 78 CENTRALIZATION_TX, 79 TX_EMPHASIS, 80 LOAD_PATTERN_HIGH, 81 PER_BIT_READ_LEVELING_TF, 82 MAX_STAGE_LIMIT 83 }; 84 85 enum hws_access_type { 86 ACCESS_TYPE_UNICAST = 0, 87 ACCESS_TYPE_MULTICAST = 1 88 }; 89 90 enum hws_algo_type { 91 ALGO_TYPE_DYNAMIC, 92 ALGO_TYPE_STATIC 93 }; 94 95 struct init_cntr_param { 96 int is_ctrl64_bit; 97 int do_mrs_phy; 98 int init_phy; 99 int msys_init; 100 }; 101 102 struct pattern_info { 103 u8 num_of_phases_tx; 104 u8 tx_burst_size; 105 u8 delay_between_bursts; 106 u8 num_of_phases_rx; 107 u32 start_addr; 108 u8 pattern_len; 109 }; 110 111 /* CL value for each frequency */ 112 struct cl_val_per_freq { 113 u8 cl_val[DDR_FREQ_LIMIT]; 114 }; 115 116 struct cs_element { 117 u8 cs_num; 118 u8 num_of_cs; 119 }; 120 121 struct mode_info { 122 /* 32 bits representing MRS bits */ 123 u32 reg_mr0[MAX_INTERFACE_NUM]; 124 u32 reg_mr1[MAX_INTERFACE_NUM]; 125 u32 reg_mr2[MAX_INTERFACE_NUM]; 126 u32 reg_m_r3[MAX_INTERFACE_NUM]; 127 /* 128 * Each element in array represent read_data_sample register delay for 129 * a specific interface. 130 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR 131 * cycles from read command until data is ready to be fetched from 132 * the PHY, when accessing CS. 133 */ 134 u32 read_data_sample[MAX_INTERFACE_NUM]; 135 /* 136 * Each element in array represent read_data_sample register delay for 137 * a specific interface. 138 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay 139 * from read command until opening the read mask, when accessing CS. 140 * This field defines the delay in DDR cycles granularity. 141 */ 142 u32 read_data_ready[MAX_INTERFACE_NUM]; 143 }; 144 145 struct hws_tip_freq_config_info { 146 u8 is_supported; 147 u8 bw_per_freq; 148 u8 rate_per_freq; 149 }; 150 151 struct hws_cs_config_info { 152 u32 cs_reg_value; 153 u32 cs_cbe_value; 154 }; 155 156 struct dfx_access { 157 u8 pipe; 158 u8 client; 159 }; 160 161 struct hws_xsb_info { 162 struct dfx_access *dfx_table; 163 }; 164 165 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table); 166 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable); 167 int hws_ddr3_tip_init_controller(u32 dev_num, 168 struct init_cntr_param *init_cntr_prm); 169 int hws_ddr3_tip_load_topology_map(u32 dev_num, 170 struct hws_topology_map *topology); 171 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); 172 int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info); 173 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); 174 u8 ddr3_tip_get_buf_min(u8 *buf_ptr); 175 u8 ddr3_tip_get_buf_max(u8 *buf_ptr); 176 177 #endif /* _DDR3_TRAINING_IP_H_ */ 178