1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _DDR3_TRAINING_HW_ALGO_H_ 8 #define _DDR3_TRAINING_HW_ALGO_H_ 9 10 int ddr3_tip_vref(u32 dev_num); 11 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id); 12 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap); 13 14 #endif /* _DDR3_TRAINING_HW_ALGO_H_ */ 15