1 /* 2 * Copyright (C) Marvell International Ltd. and its affiliates 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <spl.h> 9 #include <asm/io.h> 10 #include <asm/arch/cpu.h> 11 #include <asm/arch/soc.h> 12 13 #include "ddr3_init.h" 14 15 static u32 bist_offset = 32; 16 enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0; 17 18 static int ddr3_tip_bist_operation(u32 dev_num, 19 enum hws_access_type access_type, 20 u32 if_id, 21 enum hws_bist_operation oper_type); 22 23 /* 24 * BIST activate 25 */ 26 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 27 enum hws_access_type access_type, u32 if_num, 28 enum hws_dir direction, 29 enum hws_stress_jump addr_stress_jump, 30 enum hws_pattern_duration duration, 31 enum hws_bist_operation oper_type, 32 u32 offset, u32 cs_num, u32 pattern_addr_length) 33 { 34 u32 tx_burst_size; 35 u32 delay_between_burst; 36 u32 rd_mode, val; 37 u32 poll_cnt = 0, max_poll = 1000, i, start_if, end_if; 38 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); 39 u32 read_data[MAX_INTERFACE_NUM]; 40 struct hws_topology_map *tm = ddr3_get_topology_map(); 41 42 /* ODPG Write enable from BIST */ 43 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 44 ODPG_DATA_CONTROL_REG, 0x1, 0x1)); 45 /* ODPG Read enable/disable from BIST */ 46 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 47 ODPG_DATA_CONTROL_REG, 48 (direction == OPER_READ) ? 49 0x2 : 0, 0x2)); 50 CHECK_STATUS(ddr3_tip_load_pattern_to_odpg(dev_num, access_type, if_num, 51 pattern, offset)); 52 53 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 54 ODPG_DATA_BUF_SIZE_REG, 55 pattern_addr_length, MASK_ALL_BITS)); 56 tx_burst_size = (direction == OPER_WRITE) ? 57 pattern_table[pattern].tx_burst_size : 0; 58 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; 59 rd_mode = (direction == OPER_WRITE) ? 1 : 0; 60 CHECK_STATUS(ddr3_tip_configure_odpg 61 (dev_num, access_type, if_num, direction, 62 pattern_table[pattern].num_of_phases_tx, tx_burst_size, 63 pattern_table[pattern].num_of_phases_rx, 64 delay_between_burst, 65 rd_mode, cs_num, addr_stress_jump, duration)); 66 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 67 ODPG_PATTERN_ADDR_OFFSET_REG, 68 offset, MASK_ALL_BITS)); 69 if (oper_type == BIST_STOP) { 70 CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type, 71 if_num, BIST_STOP)); 72 } else { 73 CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type, 74 if_num, BIST_START)); 75 if (duration != DURATION_CONT) { 76 /* 77 * This pdelay is a WA, becuase polling fives "done" 78 * also the odpg did nmot finish its task 79 */ 80 if (access_type == ACCESS_TYPE_MULTICAST) { 81 start_if = 0; 82 end_if = MAX_INTERFACE_NUM - 1; 83 } else { 84 start_if = if_num; 85 end_if = if_num; 86 } 87 88 for (i = start_if; i <= end_if; i++) { 89 VALIDATE_ACTIVE(tm-> 90 if_act_mask, i); 91 92 for (poll_cnt = 0; poll_cnt < max_poll; 93 poll_cnt++) { 94 CHECK_STATUS(ddr3_tip_if_read 95 (dev_num, 96 ACCESS_TYPE_UNICAST, 97 if_num, ODPG_BIST_DONE, 98 read_data, 99 MASK_ALL_BITS)); 100 val = read_data[i]; 101 if ((val & 0x1) == 0x0) { 102 /* 103 * In SOC type devices this bit 104 * is self clear so, if it was 105 * cleared all good 106 */ 107 break; 108 } 109 } 110 111 if (poll_cnt >= max_poll) { 112 DEBUG_TRAINING_BIST_ENGINE 113 (DEBUG_LEVEL_ERROR, 114 ("Bist poll failure 2\n")); 115 CHECK_STATUS(ddr3_tip_if_write 116 (dev_num, 117 ACCESS_TYPE_UNICAST, 118 if_num, 119 ODPG_DATA_CONTROL_REG, 0, 120 MASK_ALL_BITS)); 121 return MV_FAIL; 122 } 123 } 124 125 CHECK_STATUS(ddr3_tip_bist_operation 126 (dev_num, access_type, if_num, BIST_STOP)); 127 } 128 } 129 130 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 131 ODPG_DATA_CONTROL_REG, 0, 132 MASK_ALL_BITS)); 133 134 return MV_OK; 135 } 136 137 /* 138 * BIST read result 139 */ 140 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 141 struct bist_result *pst_bist_result) 142 { 143 int ret; 144 u32 read_data[MAX_INTERFACE_NUM]; 145 struct hws_topology_map *tm = ddr3_get_topology_map(); 146 147 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) 148 return MV_NOT_SUPPORTED; 149 DEBUG_TRAINING_BIST_ENGINE(DEBUG_LEVEL_TRACE, 150 ("ddr3_tip_bist_read_result if_id %d\n", 151 if_id)); 152 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 153 ODPG_BIST_FAILED_DATA_HI_REG, read_data, 154 MASK_ALL_BITS); 155 if (ret != MV_OK) 156 return ret; 157 pst_bist_result->bist_fail_high = read_data[if_id]; 158 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 159 ODPG_BIST_FAILED_DATA_LOW_REG, read_data, 160 MASK_ALL_BITS); 161 if (ret != MV_OK) 162 return ret; 163 pst_bist_result->bist_fail_low = read_data[if_id]; 164 165 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 166 ODPG_BIST_LAST_FAIL_ADDR_REG, read_data, 167 MASK_ALL_BITS); 168 if (ret != MV_OK) 169 return ret; 170 pst_bist_result->bist_last_fail_addr = read_data[if_id]; 171 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 172 ODPG_BIST_DATA_ERROR_COUNTER_REG, read_data, 173 MASK_ALL_BITS); 174 if (ret != MV_OK) 175 return ret; 176 pst_bist_result->bist_error_cnt = read_data[if_id]; 177 178 return MV_OK; 179 } 180 181 /* 182 * BIST flow - Activate & read result 183 */ 184 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 185 u32 cs_num) 186 { 187 int ret; 188 u32 i = 0; 189 u32 win_base; 190 struct bist_result st_bist_result; 191 struct hws_topology_map *tm = ddr3_get_topology_map(); 192 193 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 194 VALIDATE_ACTIVE(tm->if_act_mask, i); 195 hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base); 196 ret = ddr3_tip_bist_activate(dev_num, pattern, 197 ACCESS_TYPE_UNICAST, 198 i, OPER_WRITE, STRESS_NONE, 199 DURATION_SINGLE, BIST_START, 200 bist_offset + win_base, 201 cs_num, 15); 202 if (ret != MV_OK) { 203 printf("ddr3_tip_bist_activate failed (0x%x)\n", ret); 204 return ret; 205 } 206 207 ret = ddr3_tip_bist_activate(dev_num, pattern, 208 ACCESS_TYPE_UNICAST, 209 i, OPER_READ, STRESS_NONE, 210 DURATION_SINGLE, BIST_START, 211 bist_offset + win_base, 212 cs_num, 15); 213 if (ret != MV_OK) { 214 printf("ddr3_tip_bist_activate failed (0x%x)\n", ret); 215 return ret; 216 } 217 218 ret = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result); 219 if (ret != MV_OK) { 220 printf("ddr3_tip_bist_read_result failed\n"); 221 return ret; 222 } 223 result[i] = st_bist_result.bist_error_cnt; 224 } 225 226 return MV_OK; 227 } 228 229 /* 230 * Set BIST Operation 231 */ 232 233 static int ddr3_tip_bist_operation(u32 dev_num, 234 enum hws_access_type access_type, 235 u32 if_id, enum hws_bist_operation oper_type) 236 { 237 if (oper_type == BIST_STOP) { 238 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 239 ODPG_BIST_DONE, 1 << 8, 1 << 8)); 240 } else { 241 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 242 ODPG_BIST_DONE, 1, 1)); 243 } 244 245 return MV_OK; 246 } 247 248 /* 249 * Print BIST result 250 */ 251 void ddr3_tip_print_bist_res(void) 252 { 253 u32 dev_num = 0; 254 u32 i; 255 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; 256 int res; 257 struct hws_topology_map *tm = ddr3_get_topology_map(); 258 259 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 260 if (IS_ACTIVE(tm->if_act_mask, i) == 0) 261 continue; 262 263 res = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result[i]); 264 if (res != MV_OK) { 265 DEBUG_TRAINING_BIST_ENGINE( 266 DEBUG_LEVEL_ERROR, 267 ("ddr3_tip_bist_read_result failed\n")); 268 return; 269 } 270 } 271 272 DEBUG_TRAINING_BIST_ENGINE( 273 DEBUG_LEVEL_INFO, 274 ("interface | error_cnt | fail_low | fail_high | fail_addr\n")); 275 276 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 277 if (IS_ACTIVE(tm->if_act_mask, i) == 278 0) 279 continue; 280 281 DEBUG_TRAINING_BIST_ENGINE( 282 DEBUG_LEVEL_INFO, 283 ("%d | 0x%08x | 0x%08x | 0x%08x | 0x%08x\n", 284 i, st_bist_result[i].bist_error_cnt, 285 st_bist_result[i].bist_fail_low, 286 st_bist_result[i].bist_fail_high, 287 st_bist_result[i].bist_last_fail_addr)); 288 } 289 } 290