1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #include <common.h> 7 #include <spl.h> 8 #include <asm/io.h> 9 #include <asm/arch/cpu.h> 10 #include <asm/arch/soc.h> 11 12 #include "ddr3_init.h" 13 14 static u32 bist_offset = 32; 15 enum hws_pattern sweep_pattern = PATTERN_KILLER_DQ0; 16 17 static int ddr3_tip_bist_operation(u32 dev_num, 18 enum hws_access_type access_type, 19 u32 if_id, 20 enum hws_bist_operation oper_type); 21 22 /* 23 * BIST activate 24 */ 25 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 26 enum hws_access_type access_type, u32 if_num, 27 enum hws_dir direction, 28 enum hws_stress_jump addr_stress_jump, 29 enum hws_pattern_duration duration, 30 enum hws_bist_operation oper_type, 31 u32 offset, u32 cs_num, u32 pattern_addr_length) 32 { 33 u32 tx_burst_size; 34 u32 delay_between_burst; 35 u32 rd_mode, val; 36 u32 poll_cnt = 0, max_poll = 1000, i, start_if, end_if; 37 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); 38 u32 read_data[MAX_INTERFACE_NUM]; 39 struct hws_topology_map *tm = ddr3_get_topology_map(); 40 41 /* ODPG Write enable from BIST */ 42 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 43 ODPG_DATA_CONTROL_REG, 0x1, 0x1)); 44 /* ODPG Read enable/disable from BIST */ 45 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 46 ODPG_DATA_CONTROL_REG, 47 (direction == OPER_READ) ? 48 0x2 : 0, 0x2)); 49 CHECK_STATUS(ddr3_tip_load_pattern_to_odpg(dev_num, access_type, if_num, 50 pattern, offset)); 51 52 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 53 ODPG_DATA_BUF_SIZE_REG, 54 pattern_addr_length, MASK_ALL_BITS)); 55 tx_burst_size = (direction == OPER_WRITE) ? 56 pattern_table[pattern].tx_burst_size : 0; 57 delay_between_burst = (direction == OPER_WRITE) ? 2 : 0; 58 rd_mode = (direction == OPER_WRITE) ? 1 : 0; 59 CHECK_STATUS(ddr3_tip_configure_odpg 60 (dev_num, access_type, if_num, direction, 61 pattern_table[pattern].num_of_phases_tx, tx_burst_size, 62 pattern_table[pattern].num_of_phases_rx, 63 delay_between_burst, 64 rd_mode, cs_num, addr_stress_jump, duration)); 65 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 66 ODPG_PATTERN_ADDR_OFFSET_REG, 67 offset, MASK_ALL_BITS)); 68 if (oper_type == BIST_STOP) { 69 CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type, 70 if_num, BIST_STOP)); 71 } else { 72 CHECK_STATUS(ddr3_tip_bist_operation(dev_num, access_type, 73 if_num, BIST_START)); 74 if (duration != DURATION_CONT) { 75 /* 76 * This pdelay is a WA, becuase polling fives "done" 77 * also the odpg did nmot finish its task 78 */ 79 if (access_type == ACCESS_TYPE_MULTICAST) { 80 start_if = 0; 81 end_if = MAX_INTERFACE_NUM - 1; 82 } else { 83 start_if = if_num; 84 end_if = if_num; 85 } 86 87 for (i = start_if; i <= end_if; i++) { 88 VALIDATE_ACTIVE(tm-> 89 if_act_mask, i); 90 91 for (poll_cnt = 0; poll_cnt < max_poll; 92 poll_cnt++) { 93 CHECK_STATUS(ddr3_tip_if_read 94 (dev_num, 95 ACCESS_TYPE_UNICAST, 96 if_num, ODPG_BIST_DONE, 97 read_data, 98 MASK_ALL_BITS)); 99 val = read_data[i]; 100 if ((val & 0x1) == 0x0) { 101 /* 102 * In SOC type devices this bit 103 * is self clear so, if it was 104 * cleared all good 105 */ 106 break; 107 } 108 } 109 110 if (poll_cnt >= max_poll) { 111 DEBUG_TRAINING_BIST_ENGINE 112 (DEBUG_LEVEL_ERROR, 113 ("Bist poll failure 2\n")); 114 CHECK_STATUS(ddr3_tip_if_write 115 (dev_num, 116 ACCESS_TYPE_UNICAST, 117 if_num, 118 ODPG_DATA_CONTROL_REG, 0, 119 MASK_ALL_BITS)); 120 return MV_FAIL; 121 } 122 } 123 124 CHECK_STATUS(ddr3_tip_bist_operation 125 (dev_num, access_type, if_num, BIST_STOP)); 126 } 127 } 128 129 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_num, 130 ODPG_DATA_CONTROL_REG, 0, 131 MASK_ALL_BITS)); 132 133 return MV_OK; 134 } 135 136 /* 137 * BIST read result 138 */ 139 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 140 struct bist_result *pst_bist_result) 141 { 142 int ret; 143 u32 read_data[MAX_INTERFACE_NUM]; 144 struct hws_topology_map *tm = ddr3_get_topology_map(); 145 146 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) 147 return MV_NOT_SUPPORTED; 148 DEBUG_TRAINING_BIST_ENGINE(DEBUG_LEVEL_TRACE, 149 ("ddr3_tip_bist_read_result if_id %d\n", 150 if_id)); 151 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 152 ODPG_BIST_FAILED_DATA_HI_REG, read_data, 153 MASK_ALL_BITS); 154 if (ret != MV_OK) 155 return ret; 156 pst_bist_result->bist_fail_high = read_data[if_id]; 157 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 158 ODPG_BIST_FAILED_DATA_LOW_REG, read_data, 159 MASK_ALL_BITS); 160 if (ret != MV_OK) 161 return ret; 162 pst_bist_result->bist_fail_low = read_data[if_id]; 163 164 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 165 ODPG_BIST_LAST_FAIL_ADDR_REG, read_data, 166 MASK_ALL_BITS); 167 if (ret != MV_OK) 168 return ret; 169 pst_bist_result->bist_last_fail_addr = read_data[if_id]; 170 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, 171 ODPG_BIST_DATA_ERROR_COUNTER_REG, read_data, 172 MASK_ALL_BITS); 173 if (ret != MV_OK) 174 return ret; 175 pst_bist_result->bist_error_cnt = read_data[if_id]; 176 177 return MV_OK; 178 } 179 180 /* 181 * BIST flow - Activate & read result 182 */ 183 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 184 u32 cs_num) 185 { 186 int ret; 187 u32 i = 0; 188 u32 win_base; 189 struct bist_result st_bist_result; 190 struct hws_topology_map *tm = ddr3_get_topology_map(); 191 192 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 193 VALIDATE_ACTIVE(tm->if_act_mask, i); 194 hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base); 195 ret = ddr3_tip_bist_activate(dev_num, pattern, 196 ACCESS_TYPE_UNICAST, 197 i, OPER_WRITE, STRESS_NONE, 198 DURATION_SINGLE, BIST_START, 199 bist_offset + win_base, 200 cs_num, 15); 201 if (ret != MV_OK) { 202 printf("ddr3_tip_bist_activate failed (0x%x)\n", ret); 203 return ret; 204 } 205 206 ret = ddr3_tip_bist_activate(dev_num, pattern, 207 ACCESS_TYPE_UNICAST, 208 i, OPER_READ, STRESS_NONE, 209 DURATION_SINGLE, BIST_START, 210 bist_offset + win_base, 211 cs_num, 15); 212 if (ret != MV_OK) { 213 printf("ddr3_tip_bist_activate failed (0x%x)\n", ret); 214 return ret; 215 } 216 217 ret = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result); 218 if (ret != MV_OK) { 219 printf("ddr3_tip_bist_read_result failed\n"); 220 return ret; 221 } 222 result[i] = st_bist_result.bist_error_cnt; 223 } 224 225 return MV_OK; 226 } 227 228 /* 229 * Set BIST Operation 230 */ 231 232 static int ddr3_tip_bist_operation(u32 dev_num, 233 enum hws_access_type access_type, 234 u32 if_id, enum hws_bist_operation oper_type) 235 { 236 if (oper_type == BIST_STOP) { 237 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 238 ODPG_BIST_DONE, 1 << 8, 1 << 8)); 239 } else { 240 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 241 ODPG_BIST_DONE, 1, 1)); 242 } 243 244 return MV_OK; 245 } 246 247 /* 248 * Print BIST result 249 */ 250 void ddr3_tip_print_bist_res(void) 251 { 252 u32 dev_num = 0; 253 u32 i; 254 struct bist_result st_bist_result[MAX_INTERFACE_NUM]; 255 int res; 256 struct hws_topology_map *tm = ddr3_get_topology_map(); 257 258 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 259 if (IS_ACTIVE(tm->if_act_mask, i) == 0) 260 continue; 261 262 res = ddr3_tip_bist_read_result(dev_num, i, &st_bist_result[i]); 263 if (res != MV_OK) { 264 DEBUG_TRAINING_BIST_ENGINE( 265 DEBUG_LEVEL_ERROR, 266 ("ddr3_tip_bist_read_result failed\n")); 267 return; 268 } 269 } 270 271 DEBUG_TRAINING_BIST_ENGINE( 272 DEBUG_LEVEL_INFO, 273 ("interface | error_cnt | fail_low | fail_high | fail_addr\n")); 274 275 for (i = 0; i < MAX_INTERFACE_NUM; i++) { 276 if (IS_ACTIVE(tm->if_act_mask, i) == 277 0) 278 continue; 279 280 DEBUG_TRAINING_BIST_ENGINE( 281 DEBUG_LEVEL_INFO, 282 ("%d | 0x%08x | 0x%08x | 0x%08x | 0x%08x\n", 283 i, st_bist_result[i].bist_error_cnt, 284 st_bist_result[i].bist_fail_low, 285 st_bist_result[i].bist_fail_high, 286 st_bist_result[i].bist_last_fail_addr)); 287 } 288 } 289