183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_LOGGING_CONFIG_H 7f1df9364SStefan Roese #define _DDR3_LOGGING_CONFIG_H 8f1df9364SStefan Roese 9f1df9364SStefan Roese #ifdef SILENT_LIB 10f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) 11f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) 12f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) 13f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) 14f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) 15f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) 16f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) 17f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) 18f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) 19f1df9364SStefan Roese #else 20f1df9364SStefan Roese #ifdef LIB_FUNCTIONAL_DEBUG_ONLY 21f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) 22f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) 23f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) \ 24f1df9364SStefan Roese if (level >= debug_training) \ 25f1df9364SStefan Roese printf s 26f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 27f1df9364SStefan Roese if (level >= debug_centralization) \ 28f1df9364SStefan Roese printf s 29f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) \ 30f1df9364SStefan Roese if (level >= debug_training_hw_alg) \ 31f1df9364SStefan Roese printf s 32f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) \ 33f1df9364SStefan Roese if (level >= debug_leveling) \ 34f1df9364SStefan Roese printf s 35f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) \ 36f1df9364SStefan Roese if (level >= debug_pbs) \ 37f1df9364SStefan Roese printf s 38f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) \ 39f1df9364SStefan Roese if (level >= debug_training_static) \ 40f1df9364SStefan Roese printf s 41f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) \ 42f1df9364SStefan Roese if (level >= debug_training_access) \ 43f1df9364SStefan Roese printf s 44f1df9364SStefan Roese #else 45f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) \ 46f1df9364SStefan Roese if (level >= debug_training_bist) \ 47f1df9364SStefan Roese printf s 48f1df9364SStefan Roese 49f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) \ 50f1df9364SStefan Roese if (level >= debug_training_ip) \ 51f1df9364SStefan Roese printf s 52f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) \ 53f1df9364SStefan Roese if (level >= debug_training) \ 54f1df9364SStefan Roese printf s 55f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 56f1df9364SStefan Roese if (level >= debug_centralization) \ 57f1df9364SStefan Roese printf s 58f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) \ 59f1df9364SStefan Roese if (level >= debug_training_hw_alg) \ 60f1df9364SStefan Roese printf s 61f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) \ 62f1df9364SStefan Roese if (level >= debug_leveling) \ 63f1df9364SStefan Roese printf s 64f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) \ 65f1df9364SStefan Roese if (level >= debug_pbs) \ 66f1df9364SStefan Roese printf s 67f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) \ 68f1df9364SStefan Roese if (level >= debug_training_static) \ 69f1df9364SStefan Roese printf s 70f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) \ 71f1df9364SStefan Roese if (level >= debug_training_access) \ 72f1df9364SStefan Roese printf s 73f1df9364SStefan Roese #endif 74f1df9364SStefan Roese #endif 75f1df9364SStefan Roese 76*2b4ffbf6SChris Packham 77f1df9364SStefan Roese /* Logging defines */ 78*2b4ffbf6SChris Packham enum mv_ddr_debug_level { 79*2b4ffbf6SChris Packham DEBUG_LEVEL_TRACE = 1, 80*2b4ffbf6SChris Packham DEBUG_LEVEL_INFO = 2, 81*2b4ffbf6SChris Packham DEBUG_LEVEL_ERROR = 3, 82*2b4ffbf6SChris Packham DEBUG_LEVEL_LAST 83*2b4ffbf6SChris Packham }; 84f1df9364SStefan Roese 85f1df9364SStefan Roese enum ddr_lib_debug_block { 86f1df9364SStefan Roese DEBUG_BLOCK_STATIC, 87f1df9364SStefan Roese DEBUG_BLOCK_TRAINING_MAIN, 88f1df9364SStefan Roese DEBUG_BLOCK_LEVELING, 89f1df9364SStefan Roese DEBUG_BLOCK_CENTRALIZATION, 90f1df9364SStefan Roese DEBUG_BLOCK_PBS, 91f1df9364SStefan Roese DEBUG_BLOCK_IP, 92f1df9364SStefan Roese DEBUG_BLOCK_BIST, 93f1df9364SStefan Roese DEBUG_BLOCK_ALG, 94f1df9364SStefan Roese DEBUG_BLOCK_DEVICE, 95f1df9364SStefan Roese DEBUG_BLOCK_ACCESS, 96f1df9364SStefan Roese DEBUG_STAGES_REG_DUMP, 97f1df9364SStefan Roese /* All excluding IP and REG_DUMP, should be enabled separatelly */ 98f1df9364SStefan Roese DEBUG_BLOCK_ALL 99f1df9364SStefan Roese }; 100f1df9364SStefan Roese 101f1df9364SStefan Roese int ddr3_tip_print_log(u32 dev_num, u32 mem_addr); 102f1df9364SStefan Roese int ddr3_tip_print_stability_log(u32 dev_num); 103f1df9364SStefan Roese 104f1df9364SStefan Roese #endif /* _DDR3_LOGGING_CONFIG_H */ 105