1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #include "ddr3_init.h"
7 #include "mv_ddr_common.h"
8 
9 static char *ddr_type = "DDR3";
10 
11 /*
12  * generic_init_controller controls D-unit configuration:
13  * '1' - dynamic D-unit configuration,
14  */
15 u8 generic_init_controller = 1;
16 
17 static int mv_ddr_training_params_set(u8 dev_num);
18 
19 /*
20  * Name:     ddr3_init - Main DDR3 Init function
21  * Desc:     This routine initialize the DDR3 MC and runs HW training.
22  * Args:     None.
23  * Notes:
24  * Returns:  None.
25  */
26 int ddr3_init(void)
27 {
28 	int status;
29 	int is_manual_cal_done;
30 
31 	/* Print mv_ddr version */
32 	mv_ddr_ver_print();
33 
34 	mv_ddr_pre_training_fixup();
35 
36 	/* SoC/Board special initializations */
37 	mv_ddr_pre_training_soc_config(ddr_type);
38 
39 	/* Set log level for training library */
40 	mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
41 
42 	mv_ddr_early_init();
43 
44 	if (mv_ddr_topology_map_update()) {
45 		printf("mv_ddr: failed to update topology\n");
46 		return MV_FAIL;
47 	}
48 
49 	if (mv_ddr_early_init2() != MV_OK)
50 		return MV_FAIL;
51 
52 	/* Set training algorithm's parameters */
53 	status = mv_ddr_training_params_set(0);
54 	if (MV_OK != status)
55 		return status;
56 
57 	mv_ddr_mc_config();
58 
59 	is_manual_cal_done = mv_ddr_manual_cal_do();
60 
61 	mv_ddr_mc_init();
62 
63 	if (!is_manual_cal_done) {
64 	}
65 
66 
67 	status = ddr3_silicon_post_init();
68 	if (MV_OK != status) {
69 		printf("DDR3 Post Init - FAILED 0x%x\n", status);
70 		return status;
71 	}
72 
73 	/* PHY initialization (Training) */
74 	status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
75 	if (MV_OK != status) {
76 		printf("%s Training Sequence - FAILED\n", ddr_type);
77 		return status;
78 	}
79 
80 #if defined(CONFIG_PHY_STATIC_PRINT)
81 	mv_ddr_phy_static_print();
82 #endif
83 
84 	/* Post MC/PHY initializations */
85 	mv_ddr_post_training_soc_config(ddr_type);
86 
87 	mv_ddr_post_training_fixup();
88 
89 	if (mv_ddr_is_ecc_ena())
90 		mv_ddr_mem_scrubbing();
91 
92 	printf("mv_ddr: completed successfully\n");
93 
94 	return MV_OK;
95 }
96 
97 /*
98  * Name:	mv_ddr_training_params_set
99  * Desc:
100  * Args:
101  * Notes:	sets internal training params
102  * Returns:
103  */
104 static int mv_ddr_training_params_set(u8 dev_num)
105 {
106 	struct tune_train_params params;
107 	int status;
108 	u32 cs_num;
109 
110 	cs_num = mv_ddr_cs_num_get();
111 
112 	/* NOTE: do not remove any field initilization */
113 	params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
114 	params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
115 	params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
116 	params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
117 	params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
118 	params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
119 	params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
120 	params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
121 	params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
122 
123 	params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
124 	params.g_dic = TUNE_TRAINING_PARAMS_DIC;
125 	params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
126 	if (cs_num == 1) {
127 		params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
128 		params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
129 	} else {
130 		params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
131 		params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
132 	}
133 
134 	status = ddr3_tip_tune_training_params(dev_num, &params);
135 	if (MV_OK != status) {
136 		printf("%s Training Sequence - FAILED\n", ddr_type);
137 		return status;
138 	}
139 
140 	return MV_OK;
141 }
142