1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2018 NXP 4 * 5 */ 6 7 #include <common.h> 8 #include <errno.h> 9 #include <asm/io.h> 10 #include <asm/arch/ddr.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/ddr.h> 13 #include <asm/arch/lpddr4_define.h> 14 #include <asm/arch/sys_proto.h> 15 16 void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) 17 { 18 int i = 0; 19 20 for (i = 0; i < num; i++) { 21 reg32_write(ddrc_cfg->reg, ddrc_cfg->val); 22 ddrc_cfg++; 23 } 24 } 25 26 void ddr_init(struct dram_timing_info *dram_timing) 27 { 28 unsigned int tmp; 29 30 debug("DDRINFO: start lpddr4 ddr init\n"); 31 /* step 1: reset */ 32 if (is_imx8mq()) { 33 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F); 34 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); 35 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); 36 } else { 37 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F); 38 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F); 39 } 40 41 mdelay(100); 42 43 debug("DDRINFO: reset done\n"); 44 /* 45 * change the clock source of dram_apb_clk_root: 46 * source 4 800MHz /4 = 200MHz 47 */ 48 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | 49 CLK_ROOT_SOURCE_SEL(4) | 50 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); 51 52 /* disable iso */ 53 reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */ 54 reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ 55 56 debug("DDRINFO: cfg clk\n"); 57 dram_pll_init(MHZ(750)); 58 59 /* 60 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, 61 * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n 62 */ 63 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); 64 65 /*step2 Configure uMCTL2's registers */ 66 debug("DDRINFO: ddrc config start\n"); 67 lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); 68 debug("DDRINFO: ddrc config done\n"); 69 70 /* 71 * step3 de-assert all reset 72 * RESET: <core_ddrc_rstn> DEASSERTED 73 * RESET: <aresetn> for Port 0 DEASSERT(0)ED 74 */ 75 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004); 76 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); 77 78 reg32_write(DDRC_DBG1(0), 0x00000000); 79 /* step4 */ 80 /* [0]dis_auto_refresh=1 */ 81 reg32_write(DDRC_RFSHCTL3(0), 0x00000011); 82 83 /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */ 84 reg32_write(DDRC_PWRCTL(0), 0x000000a8); 85 86 do { 87 tmp = reg32_read(DDRC_STAT(0)); 88 } while ((tmp & 0x33f) != 0x223); 89 90 reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ 91 92 /* step5 */ 93 reg32_write(DDRC_SWCTL(0), 0x00000000); 94 95 /* step6 */ 96 tmp = reg32_read(DDRC_MSTR2(0)); 97 if (tmp == 0x2) 98 reg32_write(DDRC_DFIMISC(0), 0x00000210); 99 else if (tmp == 0x1) 100 reg32_write(DDRC_DFIMISC(0), 0x00000110); 101 else 102 reg32_write(DDRC_DFIMISC(0), 0x00000010); 103 104 /* step7 [0]--1: disable quasi-dynamic programming */ 105 reg32_write(DDRC_SWCTL(0), 0x00000001); 106 107 /* step8 Configure LPDDR4 PHY's registers */ 108 debug("DDRINFO:ddrphy config start\n"); 109 ddr_cfg_phy(dram_timing); 110 debug("DDRINFO: ddrphy config done\n"); 111 112 /* 113 * step14 CalBusy.0 =1, indicates the calibrator is actively 114 * calibrating. Wait Calibrating done. 115 */ 116 do { 117 tmp = reg32_read(DDRPHY_CalBusy(0)); 118 } while ((tmp & 0x1)); 119 120 debug("DDRINFO:ddrphy calibration done\n"); 121 122 /* step15 [0]--0: to enable quasi-dynamic programming */ 123 reg32_write(DDRC_SWCTL(0), 0x00000000); 124 125 /* step16 */ 126 tmp = reg32_read(DDRC_MSTR2(0)); 127 if (tmp == 0x2) 128 reg32_write(DDRC_DFIMISC(0), 0x00000230); 129 else if (tmp == 0x1) 130 reg32_write(DDRC_DFIMISC(0), 0x00000130); 131 else 132 reg32_write(DDRC_DFIMISC(0), 0x00000030); 133 134 /* step17 [0]--1: disable quasi-dynamic programming */ 135 reg32_write(DDRC_SWCTL(0), 0x00000001); 136 /* step18 wait DFISTAT.dfi_init_complete to 1 */ 137 do { 138 tmp = reg32_read(DDRC_DFISTAT(0)); 139 } while ((tmp & 0x1) == 0x0); 140 141 /* step19 */ 142 reg32_write(DDRC_SWCTL(0), 0x00000000); 143 144 /* step20~22 */ 145 tmp = reg32_read(DDRC_MSTR2(0)); 146 if (tmp == 0x2) { 147 reg32_write(DDRC_DFIMISC(0), 0x00000210); 148 /* set DFIMISC.dfi_init_complete_en again */ 149 reg32_write(DDRC_DFIMISC(0), 0x00000211); 150 } else if (tmp == 0x1) { 151 reg32_write(DDRC_DFIMISC(0), 0x00000110); 152 /* set DFIMISC.dfi_init_complete_en again */ 153 reg32_write(DDRC_DFIMISC(0), 0x00000111); 154 } else { 155 /* clear DFIMISC.dfi_init_complete_en */ 156 reg32_write(DDRC_DFIMISC(0), 0x00000010); 157 /* set DFIMISC.dfi_init_complete_en again */ 158 reg32_write(DDRC_DFIMISC(0), 0x00000011); 159 } 160 161 /* step23 [5]selfref_sw=0; */ 162 reg32_write(DDRC_PWRCTL(0), 0x00000008); 163 /* step24 sw_done=1 */ 164 reg32_write(DDRC_SWCTL(0), 0x00000001); 165 166 /* step25 wait SWSTAT.sw_done_ack to 1 */ 167 do { 168 tmp = reg32_read(DDRC_SWSTAT(0)); 169 } while ((tmp & 0x1) == 0x0); 170 171 #ifdef DFI_BUG_WR 172 reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001); 173 #endif 174 /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ 175 do { 176 tmp = reg32_read(DDRC_STAT(0)); 177 } while ((tmp & 0x3) != 0x1); 178 179 /* step26 */ 180 reg32_write(DDRC_RFSHCTL3(0), 0x00000010); 181 182 /* enable port 0 */ 183 reg32_write(DDRC_PCTRL_0(0), 0x00000001); 184 debug("DDRINFO: ddrmix config done\n"); 185 186 /* save the dram timing config into memory */ 187 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE); 188 } 189