1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 */ 8 9 #include <common.h> 10 #ifdef CONFIG_PPC 11 #include <asm/fsl_law.h> 12 #endif 13 #include <div64.h> 14 15 #include <fsl_ddr.h> 16 #include <fsl_immap.h> 17 #include <asm/io.h> 18 19 /* To avoid 64-bit full-divides, we factor this here */ 20 #define ULL_2E12 2000000000000ULL 21 #define UL_5POW12 244140625UL 22 #define UL_2POW13 (1UL << 13) 23 24 #define ULL_8FS 0xFFFFFFFFULL 25 26 u32 fsl_ddr_get_version(void) 27 { 28 struct ccsr_ddr __iomem *ddr; 29 u32 ver_major_minor_errata; 30 31 ddr = (void *)_DDR_ADDR; 32 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; 33 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; 34 35 return ver_major_minor_errata; 36 } 37 38 /* 39 * Round up mclk_ps to nearest 1 ps in memory controller code 40 * if the error is 0.5ps or more. 41 * 42 * If an imprecise data rate is too high due to rounding error 43 * propagation, compute a suitably rounded mclk_ps to compute 44 * a working memory controller configuration. 45 */ 46 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) 47 { 48 unsigned int data_rate = get_ddr_freq(ctrl_num); 49 unsigned int result; 50 51 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 52 unsigned long long rem, mclk_ps = ULL_2E12; 53 54 /* Now perform the big divide, the result fits in 32-bits */ 55 rem = do_div(mclk_ps, data_rate); 56 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 57 58 return result; 59 } 60 61 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 62 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) 63 { 64 unsigned long long clks, clks_rem; 65 unsigned long data_rate = get_ddr_freq(ctrl_num); 66 67 /* Short circuit for zero picos */ 68 if (!picos) 69 return 0; 70 71 /* First multiply the time by the data rate (32x32 => 64) */ 72 clks = picos * (unsigned long long)data_rate; 73 /* 74 * Now divide by 5^12 and track the 32-bit remainder, then divide 75 * by 2*(2^12) using shifts (and updating the remainder). 76 */ 77 clks_rem = do_div(clks, UL_5POW12); 78 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 79 clks >>= 13; 80 81 /* If we had a remainder greater than the 1ps error, then round up */ 82 if (clks_rem > data_rate) 83 clks++; 84 85 /* Clamp to the maximum representable value */ 86 if (clks > ULL_8FS) 87 clks = ULL_8FS; 88 return (unsigned int) clks; 89 } 90 91 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) 92 { 93 return get_memory_clk_period_ps(ctrl_num) * mclk; 94 } 95 96 #ifdef CONFIG_PPC 97 void 98 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 99 unsigned int law_memctl, 100 unsigned int ctrl_num) 101 { 102 unsigned long long base = memctl_common_params->base_address; 103 unsigned long long size = memctl_common_params->total_mem; 104 105 /* 106 * If no DIMMs on this controller, do not proceed any further. 107 */ 108 if (!memctl_common_params->ndimms_present) { 109 return; 110 } 111 112 #if !defined(CONFIG_PHYS_64BIT) 113 if (base >= CONFIG_MAX_MEM_MAPPED) 114 return; 115 if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 116 size = CONFIG_MAX_MEM_MAPPED - base; 117 #endif 118 if (set_ddr_laws(base, size, law_memctl) < 0) { 119 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 120 law_memctl); 121 return ; 122 } 123 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 124 base, size, law_memctl); 125 } 126 127 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 128 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 129 unsigned int memctl_interleaved, 130 unsigned int ctrl_num); 131 #endif 132 133 void fsl_ddr_set_intl3r(const unsigned int granule_size) 134 { 135 #ifdef CONFIG_E6500 136 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 137 *mcintl3r = 0x80000000 | (granule_size & 0x1f); 138 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 139 #endif 140 } 141 142 u32 fsl_ddr_get_intl3r(void) 143 { 144 u32 val = 0; 145 #ifdef CONFIG_E6500 146 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 147 val = *mcintl3r; 148 #endif 149 return val; 150 } 151 152 void print_ddr_info(unsigned int start_ctrl) 153 { 154 struct ccsr_ddr __iomem *ddr = 155 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 156 157 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 158 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 159 #endif 160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 161 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); 162 #endif 163 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); 164 int cas_lat; 165 166 #if CONFIG_NUM_DDR_CONTROLLERS >= 2 167 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 168 (start_ctrl == 1)) { 169 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 170 sdram_cfg = ddr_in32(&ddr->sdram_cfg); 171 } 172 #endif 173 #if CONFIG_NUM_DDR_CONTROLLERS >= 3 174 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 175 (start_ctrl == 2)) { 176 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 177 sdram_cfg = ddr_in32(&ddr->sdram_cfg); 178 } 179 #endif 180 181 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 182 puts(" (DDR not enabled)\n"); 183 return; 184 } 185 186 puts(" (DDR"); 187 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 188 SDRAM_CFG_SDRAM_TYPE_SHIFT) { 189 case SDRAM_TYPE_DDR1: 190 puts("1"); 191 break; 192 case SDRAM_TYPE_DDR2: 193 puts("2"); 194 break; 195 case SDRAM_TYPE_DDR3: 196 puts("3"); 197 break; 198 case SDRAM_TYPE_DDR4: 199 puts("4"); 200 break; 201 default: 202 puts("?"); 203 break; 204 } 205 206 if (sdram_cfg & SDRAM_CFG_32_BE) 207 puts(", 32-bit"); 208 else if (sdram_cfg & SDRAM_CFG_16_BE) 209 puts(", 16-bit"); 210 else 211 puts(", 64-bit"); 212 213 /* Calculate CAS latency based on timing cfg values */ 214 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); 215 if (fsl_ddr_get_version() <= 0x40400) 216 cas_lat += 1; 217 else 218 cas_lat += 2; 219 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; 220 printf(", CL=%d", cas_lat >> 1); 221 if (cas_lat & 0x1) 222 puts(".5"); 223 224 if (sdram_cfg & SDRAM_CFG_ECC_EN) 225 puts(", ECC on)"); 226 else 227 puts(", ECC off)"); 228 229 #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 230 #ifdef CONFIG_E6500 231 if (*mcintl3r & 0x80000000) { 232 puts("\n"); 233 puts(" DDR Controller Interleaving Mode: "); 234 switch (*mcintl3r & 0x1f) { 235 case FSL_DDR_3WAY_1KB_INTERLEAVING: 236 puts("3-way 1KB"); 237 break; 238 case FSL_DDR_3WAY_4KB_INTERLEAVING: 239 puts("3-way 4KB"); 240 break; 241 case FSL_DDR_3WAY_8KB_INTERLEAVING: 242 puts("3-way 8KB"); 243 break; 244 default: 245 puts("3-way UNKNOWN"); 246 break; 247 } 248 } 249 #endif 250 #endif 251 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 252 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { 253 puts("\n"); 254 puts(" DDR Controller Interleaving Mode: "); 255 256 switch ((cs0_config >> 24) & 0xf) { 257 case FSL_DDR_256B_INTERLEAVING: 258 puts("256B"); 259 break; 260 case FSL_DDR_CACHE_LINE_INTERLEAVING: 261 puts("cache line"); 262 break; 263 case FSL_DDR_PAGE_INTERLEAVING: 264 puts("page"); 265 break; 266 case FSL_DDR_BANK_INTERLEAVING: 267 puts("bank"); 268 break; 269 case FSL_DDR_SUPERBANK_INTERLEAVING: 270 puts("super-bank"); 271 break; 272 default: 273 puts("invalid"); 274 break; 275 } 276 } 277 #endif 278 279 if ((sdram_cfg >> 8) & 0x7f) { 280 puts("\n"); 281 puts(" DDR Chip-Select Interleaving Mode: "); 282 switch(sdram_cfg >> 8 & 0x7f) { 283 case FSL_DDR_CS0_CS1_CS2_CS3: 284 puts("CS0+CS1+CS2+CS3"); 285 break; 286 case FSL_DDR_CS0_CS1: 287 puts("CS0+CS1"); 288 break; 289 case FSL_DDR_CS2_CS3: 290 puts("CS2+CS3"); 291 break; 292 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 293 puts("CS0+CS1 and CS2+CS3"); 294 break; 295 default: 296 puts("invalid"); 297 break; 298 } 299 } 300 } 301 302 void __weak detail_board_ddr_info(void) 303 { 304 print_ddr_info(0); 305 } 306 307 void board_add_ram_info(int use_default) 308 { 309 detail_board_ddr_info(); 310 } 311 312 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH 313 #define DDRC_DEBUG20_INIT_DONE 0x80000000 314 #define DDRC_DEBUG2_RF 0x00000040 315 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 316 unsigned int last_ctrl) 317 { 318 unsigned int i; 319 u32 ddrc_debug20; 320 u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; 321 u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; 322 struct ccsr_ddr __iomem *ddr; 323 324 for (i = first_ctrl; i <= last_ctrl; i++) { 325 switch (i) { 326 case 0: 327 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 328 break; 329 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 330 case 1: 331 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 332 break; 333 #endif 334 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 335 case 2: 336 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 337 break; 338 #endif 339 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 340 case 3: 341 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 342 break; 343 #endif 344 default: 345 printf("%s unexpected ctrl = %u\n", __func__, i); 346 return; 347 } 348 ddrc_debug20 = ddr_in32(&ddr->debug[19]); 349 ddrc_debug2_p[i] = &ddr->debug[1]; 350 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { 351 /* keep polling until DDRC init is done */ 352 udelay(100); 353 ddrc_debug20 = ddr_in32(&ddr->debug[19]); 354 } 355 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; 356 } 357 /* 358 * Sync refresh 359 * This is put together to make sure the refresh reqeusts are sent 360 * closely to each other. 361 */ 362 for (i = first_ctrl; i <= last_ctrl; i++) 363 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); 364 } 365 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ 366