15614e71bSYork Sun /* 234e026f9SYork Sun * Copyright 2008-2014 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45614e71bSYork Sun * This program is free software; you can redistribute it and/or 55614e71bSYork Sun * modify it under the terms of the GNU General Public License 65614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 75614e71bSYork Sun */ 85614e71bSYork Sun 95614e71bSYork Sun #include <common.h> 109ac4ffbdSYork Sun #ifdef CONFIG_PPC 115614e71bSYork Sun #include <asm/fsl_law.h> 129ac4ffbdSYork Sun #endif 135614e71bSYork Sun #include <div64.h> 145614e71bSYork Sun 155614e71bSYork Sun #include <fsl_ddr.h> 169a17eb5bSYork Sun #include <fsl_immap.h> 175614e71bSYork Sun #include <asm/io.h> 185614e71bSYork Sun 195614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 205614e71bSYork Sun #define ULL_2E12 2000000000000ULL 215614e71bSYork Sun #define UL_5POW12 244140625UL 225614e71bSYork Sun #define UL_2POW13 (1UL << 13) 235614e71bSYork Sun 245614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 255614e71bSYork Sun 2634e026f9SYork Sun u32 fsl_ddr_get_version(void) 2734e026f9SYork Sun { 2834e026f9SYork Sun struct ccsr_ddr __iomem *ddr; 2934e026f9SYork Sun u32 ver_major_minor_errata; 3034e026f9SYork Sun 3134e026f9SYork Sun ddr = (void *)_DDR_ADDR; 3234e026f9SYork Sun ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; 3334e026f9SYork Sun ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; 3434e026f9SYork Sun 3534e026f9SYork Sun return ver_major_minor_errata; 3634e026f9SYork Sun } 3734e026f9SYork Sun 385614e71bSYork Sun /* 395614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 405614e71bSYork Sun * if the error is 0.5ps or more. 415614e71bSYork Sun * 425614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 435614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 445614e71bSYork Sun * a working memory controller configuration. 455614e71bSYork Sun */ 4603e664d8SYork Sun unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) 475614e71bSYork Sun { 4803e664d8SYork Sun unsigned int data_rate = get_ddr_freq(ctrl_num); 495614e71bSYork Sun unsigned int result; 505614e71bSYork Sun 515614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 525614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 535614e71bSYork Sun 545614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 555614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 565614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 575614e71bSYork Sun 585614e71bSYork Sun return result; 595614e71bSYork Sun } 605614e71bSYork Sun 615614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 6203e664d8SYork Sun unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) 635614e71bSYork Sun { 645614e71bSYork Sun unsigned long long clks, clks_rem; 6503e664d8SYork Sun unsigned long data_rate = get_ddr_freq(ctrl_num); 665614e71bSYork Sun 675614e71bSYork Sun /* Short circuit for zero picos */ 685614e71bSYork Sun if (!picos) 695614e71bSYork Sun return 0; 705614e71bSYork Sun 715614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 725614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 735614e71bSYork Sun /* 745614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 755614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 765614e71bSYork Sun */ 775614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 785614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 795614e71bSYork Sun clks >>= 13; 805614e71bSYork Sun 815614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 825614e71bSYork Sun if (clks_rem > data_rate) 835614e71bSYork Sun clks++; 845614e71bSYork Sun 855614e71bSYork Sun /* Clamp to the maximum representable value */ 865614e71bSYork Sun if (clks > ULL_8FS) 875614e71bSYork Sun clks = ULL_8FS; 885614e71bSYork Sun return (unsigned int) clks; 895614e71bSYork Sun } 905614e71bSYork Sun 9103e664d8SYork Sun unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) 925614e71bSYork Sun { 9303e664d8SYork Sun return get_memory_clk_period_ps(ctrl_num) * mclk; 945614e71bSYork Sun } 955614e71bSYork Sun 969ac4ffbdSYork Sun #ifdef CONFIG_PPC 975614e71bSYork Sun void 985614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 995614e71bSYork Sun unsigned int law_memctl, 1005614e71bSYork Sun unsigned int ctrl_num) 1015614e71bSYork Sun { 1025614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 1035614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 1045614e71bSYork Sun 1055614e71bSYork Sun /* 1065614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 1075614e71bSYork Sun */ 1085614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 1095614e71bSYork Sun return; 1105614e71bSYork Sun } 1115614e71bSYork Sun 1125614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 1135614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 1145614e71bSYork Sun return; 1155614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 1165614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 1175614e71bSYork Sun #endif 1185614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 1195614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 1205614e71bSYork Sun law_memctl); 1215614e71bSYork Sun return ; 1225614e71bSYork Sun } 1235614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 1245614e71bSYork Sun base, size, law_memctl); 1255614e71bSYork Sun } 1265614e71bSYork Sun 1275614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 1285614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1295614e71bSYork Sun unsigned int memctl_interleaved, 1305614e71bSYork Sun unsigned int ctrl_num); 1319ac4ffbdSYork Sun #endif 1325614e71bSYork Sun 1335614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 1345614e71bSYork Sun { 1355614e71bSYork Sun #ifdef CONFIG_E6500 1365614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1375614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 1385614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 1395614e71bSYork Sun #endif 1405614e71bSYork Sun } 1415614e71bSYork Sun 1425614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 1435614e71bSYork Sun { 1445614e71bSYork Sun u32 val = 0; 1455614e71bSYork Sun #ifdef CONFIG_E6500 1465614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1475614e71bSYork Sun val = *mcintl3r; 1485614e71bSYork Sun #endif 1495614e71bSYork Sun return val; 1505614e71bSYork Sun } 1515614e71bSYork Sun 1521d71efbbSYork Sun void print_ddr_info(unsigned int start_ctrl) 1535614e71bSYork Sun { 1549a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 1559a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 1565614e71bSYork Sun 1575614e71bSYork Sun #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 1585614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1595614e71bSYork Sun #endif 1605614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 1614e5b1bd0SYork Sun uint32_t cs0_config = ddr_in32(&ddr->cs0_config); 1625614e71bSYork Sun #endif 1634e5b1bd0SYork Sun uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1645614e71bSYork Sun int cas_lat; 1655614e71bSYork Sun 1665614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 2 1671d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1681d71efbbSYork Sun (start_ctrl == 1)) { 1695614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 1704e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1715614e71bSYork Sun } 1725614e71bSYork Sun #endif 1735614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 3 1741d71efbbSYork Sun if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || 1751d71efbbSYork Sun (start_ctrl == 2)) { 1765614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 1774e5b1bd0SYork Sun sdram_cfg = ddr_in32(&ddr->sdram_cfg); 1785614e71bSYork Sun } 1795614e71bSYork Sun #endif 1801d71efbbSYork Sun 1811d71efbbSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 1821d71efbbSYork Sun puts(" (DDR not enabled)\n"); 1831d71efbbSYork Sun return; 1841d71efbbSYork Sun } 1851d71efbbSYork Sun 1865614e71bSYork Sun puts(" (DDR"); 1875614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 1885614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 1895614e71bSYork Sun case SDRAM_TYPE_DDR1: 1905614e71bSYork Sun puts("1"); 1915614e71bSYork Sun break; 1925614e71bSYork Sun case SDRAM_TYPE_DDR2: 1935614e71bSYork Sun puts("2"); 1945614e71bSYork Sun break; 1955614e71bSYork Sun case SDRAM_TYPE_DDR3: 1965614e71bSYork Sun puts("3"); 1975614e71bSYork Sun break; 19834e026f9SYork Sun case SDRAM_TYPE_DDR4: 19934e026f9SYork Sun puts("4"); 20034e026f9SYork Sun break; 2015614e71bSYork Sun default: 2025614e71bSYork Sun puts("?"); 2035614e71bSYork Sun break; 2045614e71bSYork Sun } 2055614e71bSYork Sun 2065614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 2075614e71bSYork Sun puts(", 32-bit"); 2085614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 2095614e71bSYork Sun puts(", 16-bit"); 2105614e71bSYork Sun else 2115614e71bSYork Sun puts(", 64-bit"); 2125614e71bSYork Sun 2135614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 21434e026f9SYork Sun cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); 21534e026f9SYork Sun if (fsl_ddr_get_version() <= 0x40400) 21634e026f9SYork Sun cas_lat += 1; 21734e026f9SYork Sun else 21834e026f9SYork Sun cas_lat += 2; 21934e026f9SYork Sun cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; 2205614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 2215614e71bSYork Sun if (cas_lat & 0x1) 2225614e71bSYork Sun puts(".5"); 2235614e71bSYork Sun 2245614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 2255614e71bSYork Sun puts(", ECC on)"); 2265614e71bSYork Sun else 2275614e71bSYork Sun puts(", ECC off)"); 2285614e71bSYork Sun 2295614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 2305614e71bSYork Sun #ifdef CONFIG_E6500 2315614e71bSYork Sun if (*mcintl3r & 0x80000000) { 2325614e71bSYork Sun puts("\n"); 2335614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2345614e71bSYork Sun switch (*mcintl3r & 0x1f) { 2355614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 2365614e71bSYork Sun puts("3-way 1KB"); 2375614e71bSYork Sun break; 2385614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 2395614e71bSYork Sun puts("3-way 4KB"); 2405614e71bSYork Sun break; 2415614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 2425614e71bSYork Sun puts("3-way 8KB"); 2435614e71bSYork Sun break; 2445614e71bSYork Sun default: 2455614e71bSYork Sun puts("3-way UNKNOWN"); 2465614e71bSYork Sun break; 2475614e71bSYork Sun } 2485614e71bSYork Sun } 2495614e71bSYork Sun #endif 2505614e71bSYork Sun #endif 2515614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 2521d71efbbSYork Sun if ((cs0_config & 0x20000000) && (start_ctrl == 0)) { 2535614e71bSYork Sun puts("\n"); 2545614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2555614e71bSYork Sun 2565614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 2576b1e1254SYork Sun case FSL_DDR_256B_INTERLEAVING: 2586b1e1254SYork Sun puts("256B"); 2596b1e1254SYork Sun break; 2605614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 2615614e71bSYork Sun puts("cache line"); 2625614e71bSYork Sun break; 2635614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 2645614e71bSYork Sun puts("page"); 2655614e71bSYork Sun break; 2665614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 2675614e71bSYork Sun puts("bank"); 2685614e71bSYork Sun break; 2695614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 2705614e71bSYork Sun puts("super-bank"); 2715614e71bSYork Sun break; 2725614e71bSYork Sun default: 2735614e71bSYork Sun puts("invalid"); 2745614e71bSYork Sun break; 2755614e71bSYork Sun } 2765614e71bSYork Sun } 2775614e71bSYork Sun #endif 2785614e71bSYork Sun 2795614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 2805614e71bSYork Sun puts("\n"); 2815614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 2825614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 2835614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 2845614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 2855614e71bSYork Sun break; 2865614e71bSYork Sun case FSL_DDR_CS0_CS1: 2875614e71bSYork Sun puts("CS0+CS1"); 2885614e71bSYork Sun break; 2895614e71bSYork Sun case FSL_DDR_CS2_CS3: 2905614e71bSYork Sun puts("CS2+CS3"); 2915614e71bSYork Sun break; 2925614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2935614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 2945614e71bSYork Sun break; 2955614e71bSYork Sun default: 2965614e71bSYork Sun puts("invalid"); 2975614e71bSYork Sun break; 2985614e71bSYork Sun } 2995614e71bSYork Sun } 3005614e71bSYork Sun } 3011d71efbbSYork Sun 3021d71efbbSYork Sun void __weak detail_board_ddr_info(void) 3031d71efbbSYork Sun { 3041d71efbbSYork Sun print_ddr_info(0); 3051d71efbbSYork Sun } 3061d71efbbSYork Sun 3071d71efbbSYork Sun void board_add_ram_info(int use_default) 3081d71efbbSYork Sun { 3091d71efbbSYork Sun detail_board_ddr_info(); 3101d71efbbSYork Sun } 311*e32d59a2SYork Sun 312*e32d59a2SYork Sun #ifdef CONFIG_FSL_DDR_SYNC_REFRESH 313*e32d59a2SYork Sun #define DDRC_DEBUG20_INIT_DONE 0x80000000 314*e32d59a2SYork Sun #define DDRC_DEBUG2_RF 0x00000040 315*e32d59a2SYork Sun void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, 316*e32d59a2SYork Sun unsigned int last_ctrl) 317*e32d59a2SYork Sun { 318*e32d59a2SYork Sun unsigned int i; 319*e32d59a2SYork Sun u32 ddrc_debug20; 320*e32d59a2SYork Sun u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; 321*e32d59a2SYork Sun u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; 322*e32d59a2SYork Sun struct ccsr_ddr __iomem *ddr; 323*e32d59a2SYork Sun 324*e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) { 325*e32d59a2SYork Sun switch (i) { 326*e32d59a2SYork Sun case 0: 327*e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 328*e32d59a2SYork Sun break; 329*e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) 330*e32d59a2SYork Sun case 1: 331*e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 332*e32d59a2SYork Sun break; 333*e32d59a2SYork Sun #endif 334*e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) 335*e32d59a2SYork Sun case 2: 336*e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 337*e32d59a2SYork Sun break; 338*e32d59a2SYork Sun #endif 339*e32d59a2SYork Sun #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) 340*e32d59a2SYork Sun case 3: 341*e32d59a2SYork Sun ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 342*e32d59a2SYork Sun break; 343*e32d59a2SYork Sun #endif 344*e32d59a2SYork Sun default: 345*e32d59a2SYork Sun printf("%s unexpected ctrl = %u\n", __func__, i); 346*e32d59a2SYork Sun return; 347*e32d59a2SYork Sun } 348*e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 349*e32d59a2SYork Sun ddrc_debug2_p[i] = &ddr->debug[1]; 350*e32d59a2SYork Sun while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { 351*e32d59a2SYork Sun /* keep polling until DDRC init is done */ 352*e32d59a2SYork Sun udelay(100); 353*e32d59a2SYork Sun ddrc_debug20 = ddr_in32(&ddr->debug[19]); 354*e32d59a2SYork Sun } 355*e32d59a2SYork Sun ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; 356*e32d59a2SYork Sun } 357*e32d59a2SYork Sun /* 358*e32d59a2SYork Sun * Sync refresh 359*e32d59a2SYork Sun * This is put together to make sure the refresh reqeusts are sent 360*e32d59a2SYork Sun * closely to each other. 361*e32d59a2SYork Sun */ 362*e32d59a2SYork Sun for (i = first_ctrl; i <= last_ctrl; i++) 363*e32d59a2SYork Sun ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); 364*e32d59a2SYork Sun } 365*e32d59a2SYork Sun #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ 366