15614e71bSYork Sun /* 25614e71bSYork Sun * Copyright 2008-2012 Freescale Semiconductor, Inc. 35614e71bSYork Sun * 45614e71bSYork Sun * This program is free software; you can redistribute it and/or 55614e71bSYork Sun * modify it under the terms of the GNU General Public License 65614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 75614e71bSYork Sun */ 85614e71bSYork Sun 95614e71bSYork Sun #include <common.h> 105614e71bSYork Sun #include <asm/fsl_law.h> 115614e71bSYork Sun #include <div64.h> 125614e71bSYork Sun 135614e71bSYork Sun #include <fsl_ddr.h> 14*9a17eb5bSYork Sun #include <fsl_immap.h> 155614e71bSYork Sun #include <asm/io.h> 165614e71bSYork Sun 175614e71bSYork Sun /* To avoid 64-bit full-divides, we factor this here */ 185614e71bSYork Sun #define ULL_2E12 2000000000000ULL 195614e71bSYork Sun #define UL_5POW12 244140625UL 205614e71bSYork Sun #define UL_2POW13 (1UL << 13) 215614e71bSYork Sun 225614e71bSYork Sun #define ULL_8FS 0xFFFFFFFFULL 235614e71bSYork Sun 245614e71bSYork Sun /* 255614e71bSYork Sun * Round up mclk_ps to nearest 1 ps in memory controller code 265614e71bSYork Sun * if the error is 0.5ps or more. 275614e71bSYork Sun * 285614e71bSYork Sun * If an imprecise data rate is too high due to rounding error 295614e71bSYork Sun * propagation, compute a suitably rounded mclk_ps to compute 305614e71bSYork Sun * a working memory controller configuration. 315614e71bSYork Sun */ 325614e71bSYork Sun unsigned int get_memory_clk_period_ps(void) 335614e71bSYork Sun { 345614e71bSYork Sun unsigned int data_rate = get_ddr_freq(0); 355614e71bSYork Sun unsigned int result; 365614e71bSYork Sun 375614e71bSYork Sun /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ 385614e71bSYork Sun unsigned long long rem, mclk_ps = ULL_2E12; 395614e71bSYork Sun 405614e71bSYork Sun /* Now perform the big divide, the result fits in 32-bits */ 415614e71bSYork Sun rem = do_div(mclk_ps, data_rate); 425614e71bSYork Sun result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; 435614e71bSYork Sun 445614e71bSYork Sun return result; 455614e71bSYork Sun } 465614e71bSYork Sun 475614e71bSYork Sun /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ 485614e71bSYork Sun unsigned int picos_to_mclk(unsigned int picos) 495614e71bSYork Sun { 505614e71bSYork Sun unsigned long long clks, clks_rem; 515614e71bSYork Sun unsigned long data_rate = get_ddr_freq(0); 525614e71bSYork Sun 535614e71bSYork Sun /* Short circuit for zero picos */ 545614e71bSYork Sun if (!picos) 555614e71bSYork Sun return 0; 565614e71bSYork Sun 575614e71bSYork Sun /* First multiply the time by the data rate (32x32 => 64) */ 585614e71bSYork Sun clks = picos * (unsigned long long)data_rate; 595614e71bSYork Sun /* 605614e71bSYork Sun * Now divide by 5^12 and track the 32-bit remainder, then divide 615614e71bSYork Sun * by 2*(2^12) using shifts (and updating the remainder). 625614e71bSYork Sun */ 635614e71bSYork Sun clks_rem = do_div(clks, UL_5POW12); 645614e71bSYork Sun clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; 655614e71bSYork Sun clks >>= 13; 665614e71bSYork Sun 675614e71bSYork Sun /* If we had a remainder greater than the 1ps error, then round up */ 685614e71bSYork Sun if (clks_rem > data_rate) 695614e71bSYork Sun clks++; 705614e71bSYork Sun 715614e71bSYork Sun /* Clamp to the maximum representable value */ 725614e71bSYork Sun if (clks > ULL_8FS) 735614e71bSYork Sun clks = ULL_8FS; 745614e71bSYork Sun return (unsigned int) clks; 755614e71bSYork Sun } 765614e71bSYork Sun 775614e71bSYork Sun unsigned int mclk_to_picos(unsigned int mclk) 785614e71bSYork Sun { 795614e71bSYork Sun return get_memory_clk_period_ps() * mclk; 805614e71bSYork Sun } 815614e71bSYork Sun 825614e71bSYork Sun void 835614e71bSYork Sun __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 845614e71bSYork Sun unsigned int law_memctl, 855614e71bSYork Sun unsigned int ctrl_num) 865614e71bSYork Sun { 875614e71bSYork Sun unsigned long long base = memctl_common_params->base_address; 885614e71bSYork Sun unsigned long long size = memctl_common_params->total_mem; 895614e71bSYork Sun 905614e71bSYork Sun /* 915614e71bSYork Sun * If no DIMMs on this controller, do not proceed any further. 925614e71bSYork Sun */ 935614e71bSYork Sun if (!memctl_common_params->ndimms_present) { 945614e71bSYork Sun return; 955614e71bSYork Sun } 965614e71bSYork Sun 975614e71bSYork Sun #if !defined(CONFIG_PHYS_64BIT) 985614e71bSYork Sun if (base >= CONFIG_MAX_MEM_MAPPED) 995614e71bSYork Sun return; 1005614e71bSYork Sun if ((base + size) >= CONFIG_MAX_MEM_MAPPED) 1015614e71bSYork Sun size = CONFIG_MAX_MEM_MAPPED - base; 1025614e71bSYork Sun #endif 1035614e71bSYork Sun if (set_ddr_laws(base, size, law_memctl) < 0) { 1045614e71bSYork Sun printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, 1055614e71bSYork Sun law_memctl); 1065614e71bSYork Sun return ; 1075614e71bSYork Sun } 1085614e71bSYork Sun debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", 1095614e71bSYork Sun base, size, law_memctl); 1105614e71bSYork Sun } 1115614e71bSYork Sun 1125614e71bSYork Sun __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void 1135614e71bSYork Sun fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, 1145614e71bSYork Sun unsigned int memctl_interleaved, 1155614e71bSYork Sun unsigned int ctrl_num); 1165614e71bSYork Sun 1175614e71bSYork Sun void fsl_ddr_set_intl3r(const unsigned int granule_size) 1185614e71bSYork Sun { 1195614e71bSYork Sun #ifdef CONFIG_E6500 1205614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1215614e71bSYork Sun *mcintl3r = 0x80000000 | (granule_size & 0x1f); 1225614e71bSYork Sun debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); 1235614e71bSYork Sun #endif 1245614e71bSYork Sun } 1255614e71bSYork Sun 1265614e71bSYork Sun u32 fsl_ddr_get_intl3r(void) 1275614e71bSYork Sun { 1285614e71bSYork Sun u32 val = 0; 1295614e71bSYork Sun #ifdef CONFIG_E6500 1305614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1315614e71bSYork Sun val = *mcintl3r; 1325614e71bSYork Sun #endif 1335614e71bSYork Sun return val; 1345614e71bSYork Sun } 1355614e71bSYork Sun 1365614e71bSYork Sun void board_add_ram_info(int use_default) 1375614e71bSYork Sun { 138*9a17eb5bSYork Sun struct ccsr_ddr __iomem *ddr = 139*9a17eb5bSYork Sun (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 1405614e71bSYork Sun 1415614e71bSYork Sun #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) 1425614e71bSYork Sun u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); 1435614e71bSYork Sun #endif 1445614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 1455614e71bSYork Sun uint32_t cs0_config = in_be32(&ddr->cs0_config); 1465614e71bSYork Sun #endif 1475614e71bSYork Sun uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); 1485614e71bSYork Sun int cas_lat; 1495614e71bSYork Sun 1505614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 2 1515614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 1525614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; 1535614e71bSYork Sun sdram_cfg = in_be32(&ddr->sdram_cfg); 1545614e71bSYork Sun } 1555614e71bSYork Sun #endif 1565614e71bSYork Sun #if CONFIG_NUM_DDR_CONTROLLERS >= 3 1575614e71bSYork Sun if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { 1585614e71bSYork Sun ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; 1595614e71bSYork Sun sdram_cfg = in_be32(&ddr->sdram_cfg); 1605614e71bSYork Sun } 1615614e71bSYork Sun #endif 1625614e71bSYork Sun puts(" (DDR"); 1635614e71bSYork Sun switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 1645614e71bSYork Sun SDRAM_CFG_SDRAM_TYPE_SHIFT) { 1655614e71bSYork Sun case SDRAM_TYPE_DDR1: 1665614e71bSYork Sun puts("1"); 1675614e71bSYork Sun break; 1685614e71bSYork Sun case SDRAM_TYPE_DDR2: 1695614e71bSYork Sun puts("2"); 1705614e71bSYork Sun break; 1715614e71bSYork Sun case SDRAM_TYPE_DDR3: 1725614e71bSYork Sun puts("3"); 1735614e71bSYork Sun break; 1745614e71bSYork Sun default: 1755614e71bSYork Sun puts("?"); 1765614e71bSYork Sun break; 1775614e71bSYork Sun } 1785614e71bSYork Sun 1795614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_32_BE) 1805614e71bSYork Sun puts(", 32-bit"); 1815614e71bSYork Sun else if (sdram_cfg & SDRAM_CFG_16_BE) 1825614e71bSYork Sun puts(", 16-bit"); 1835614e71bSYork Sun else 1845614e71bSYork Sun puts(", 64-bit"); 1855614e71bSYork Sun 1865614e71bSYork Sun /* Calculate CAS latency based on timing cfg values */ 1875614e71bSYork Sun cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; 1885614e71bSYork Sun if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) 1895614e71bSYork Sun cas_lat += (8 << 1); 1905614e71bSYork Sun printf(", CL=%d", cas_lat >> 1); 1915614e71bSYork Sun if (cas_lat & 0x1) 1925614e71bSYork Sun puts(".5"); 1935614e71bSYork Sun 1945614e71bSYork Sun if (sdram_cfg & SDRAM_CFG_ECC_EN) 1955614e71bSYork Sun puts(", ECC on)"); 1965614e71bSYork Sun else 1975614e71bSYork Sun puts(", ECC off)"); 1985614e71bSYork Sun 1995614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 2005614e71bSYork Sun #ifdef CONFIG_E6500 2015614e71bSYork Sun if (*mcintl3r & 0x80000000) { 2025614e71bSYork Sun puts("\n"); 2035614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2045614e71bSYork Sun switch (*mcintl3r & 0x1f) { 2055614e71bSYork Sun case FSL_DDR_3WAY_1KB_INTERLEAVING: 2065614e71bSYork Sun puts("3-way 1KB"); 2075614e71bSYork Sun break; 2085614e71bSYork Sun case FSL_DDR_3WAY_4KB_INTERLEAVING: 2095614e71bSYork Sun puts("3-way 4KB"); 2105614e71bSYork Sun break; 2115614e71bSYork Sun case FSL_DDR_3WAY_8KB_INTERLEAVING: 2125614e71bSYork Sun puts("3-way 8KB"); 2135614e71bSYork Sun break; 2145614e71bSYork Sun default: 2155614e71bSYork Sun puts("3-way UNKNOWN"); 2165614e71bSYork Sun break; 2175614e71bSYork Sun } 2185614e71bSYork Sun } 2195614e71bSYork Sun #endif 2205614e71bSYork Sun #endif 2215614e71bSYork Sun #if (CONFIG_NUM_DDR_CONTROLLERS >= 2) 2225614e71bSYork Sun if (cs0_config & 0x20000000) { 2235614e71bSYork Sun puts("\n"); 2245614e71bSYork Sun puts(" DDR Controller Interleaving Mode: "); 2255614e71bSYork Sun 2265614e71bSYork Sun switch ((cs0_config >> 24) & 0xf) { 2275614e71bSYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 2285614e71bSYork Sun puts("cache line"); 2295614e71bSYork Sun break; 2305614e71bSYork Sun case FSL_DDR_PAGE_INTERLEAVING: 2315614e71bSYork Sun puts("page"); 2325614e71bSYork Sun break; 2335614e71bSYork Sun case FSL_DDR_BANK_INTERLEAVING: 2345614e71bSYork Sun puts("bank"); 2355614e71bSYork Sun break; 2365614e71bSYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 2375614e71bSYork Sun puts("super-bank"); 2385614e71bSYork Sun break; 2395614e71bSYork Sun default: 2405614e71bSYork Sun puts("invalid"); 2415614e71bSYork Sun break; 2425614e71bSYork Sun } 2435614e71bSYork Sun } 2445614e71bSYork Sun #endif 2455614e71bSYork Sun 2465614e71bSYork Sun if ((sdram_cfg >> 8) & 0x7f) { 2475614e71bSYork Sun puts("\n"); 2485614e71bSYork Sun puts(" DDR Chip-Select Interleaving Mode: "); 2495614e71bSYork Sun switch(sdram_cfg >> 8 & 0x7f) { 2505614e71bSYork Sun case FSL_DDR_CS0_CS1_CS2_CS3: 2515614e71bSYork Sun puts("CS0+CS1+CS2+CS3"); 2525614e71bSYork Sun break; 2535614e71bSYork Sun case FSL_DDR_CS0_CS1: 2545614e71bSYork Sun puts("CS0+CS1"); 2555614e71bSYork Sun break; 2565614e71bSYork Sun case FSL_DDR_CS2_CS3: 2575614e71bSYork Sun puts("CS2+CS3"); 2585614e71bSYork Sun break; 2595614e71bSYork Sun case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2605614e71bSYork Sun puts("CS0+CS1 and CS2+CS3"); 2615614e71bSYork Sun break; 2625614e71bSYork Sun default: 2635614e71bSYork Sun puts("invalid"); 2645614e71bSYork Sun break; 2655614e71bSYork Sun } 2665614e71bSYork Sun } 2675614e71bSYork Sun } 268